Attia, O., K. Townsend, P. Jones, and J. Zambreno,
"A Reconfigurable Architecture for the Detection of Strongly Connected Components",
ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 9, issue 2, December, 2015.
AttTow15A.pdf (1.33 MB) Nelson, C., K. Townsend, O. Attia, P. Jones, and J. Zambreno,
"RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing",
IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, issue 10, 2016.
NelTow16A.pdf (1.19 MB) Sun, S., M. Monga, P. Jones, and J. Zambreno,
"An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs",
IEEE Transactions on Circuits and Systems-I (TCAS-I), vol. 59, no. 1, pp. 113-123, 2012.
SunMon12A.pdf (840.43 KB) Kumar, C., S. Vyas, R. Cytron, C. Gill, J. Zambreno, and P. Jones,
"Hardware-Software Architecture for Priority Queue Management in Real-time and Embedded Systems",
International Journal of Embedded Systems (IJES), vol. 6, no. 4, pp. 319-334, 2014.
KumVya13B.pdf (868.27 KB) Vyas, S., C. Kumar, J. Zambreno, C. Gill, R. Cytron, and P. Jones,
"An FPGA-based Plant-on-Chip Platform for Cyber-Physical System Analysis",
IEEE Embedded Systems Letters (ESL), vol. 6, no. 1, pp. 4-7, 2014.
VyaKum13A.pdf (691.9 KB) Johnson, T., D. Roggow, P. Jones, and J. Zambreno,
"An FPGA Architecture for the Recovery of WPA/WPA2 Keys",
Journal of Circuits, Systems, and Computers (JCSC), vol. 24, issue 7, 2015.
JohRog15A.pdf (1.42 MB) Qasaimeh, M., K. Denolf, A. Khodamoradi, M. Blott, J. Lo, L. Halder, K. Vissers, J. Zambreno, and P. Jones,
"Benchmarking Vision Kernels and Neural Network Inference Accelerators on Embedded Platforms",
Journal of Systems Architecture, vol. 113, February, 2021.
QasDen20A.pdf (671.95 KB)