|Title||ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation|
|Publication Type||Conference Papers|
|Authors||Pivezhandi, M., P. Jones, and J. Zambreno|
|Conference Name||Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP)|
In this paper, we present an FPGA-based architecture for histogram generation to support event-based camera optical flow calculation. Our proposed histogram generation mechanism reduces memory and logic resources by storing the time difference between consecutive events, instead of the absolute time of each event. Additionally, we explore the trade-off between system resource usage and histogram accuracy as a function of the precision at which time is encoded. Our results show that across three event-based camera benchmarks we can reduce the encoding of time from 32 to 7 bits with a loss of only approximately 3% in histogram accuracy. In comparison to a software implementation, our architecture shows a significant speedup.