|Title||k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator|
|Publication Type||Conference Papers|
|Authors||Townsend, K., S. Sun, T. Johnson, O. Attia, P. Jones, and J. Zambreno|
|Conference Name||Proceedings of the IEEE International Conference on Electro/Information Technology (EIT)|
Text classification is an important enabling technology for a wide range of applications such as Internet search, email filtering, network intrusion detection, and data mining electronic documents in general. The k Nearest Neighbors (k-NN) text classification algorithm is among the most accurate classification approaches, but is also among the most computationally expensive. In this paper, we propose accelerating k-NN using a novel reconfigurable hardware based architecture. More specifically, we accelerate a k-NN application’s core with an FPGA-based sparse matrix vector multiplication coprocessor. On average our implementation shows a speed up factor of 15 over a naive single threaded CPU implementation of k-NN text classification for our datasets, and a speed up factor of 1.5 over a 32-threaded parallelized CPU implementation.