Cache Design for Mixed Critical Real-Time Systems
| Authors | Chetan Kumar, Sudhanshu Vyas, Ron Cytron, Christopher Gill, Joseph Zambreno, and Phillip Jones |
|---|---|
| Type | Conference Paper |
| Published in | Proceedings of the International Conference on Computer Design (ICCD) |
| Date | October 2014 |
Abstract
Shared caches in mixed criticality systems are a source of interference for safety critical tasks. Shared memory not only leads to worst-case execution time (WCET) pessimism, but also affects the response time of safety critical tasks. In this paper, we present a criticality aware cache design which implements a Least Critical (LC) cache replacement policy, where a least recently used non-critical cache line is replaced during a cache miss. The cache acts as a Least Recently Used (LRU) cache if there are no critical lines or if all cache lines are critical in a set. In our design, data within a certain address space is given higher preference in the cache. These critical address spaces are configured using critical address range (CAR) registers. The new cache design was implemented in a Leon3 processor core, a 32bit processor compliant with the SPARC V8 architecture. Experimental results are presented that illustrate the impact of the Least Critical cache replacement policy on the response time of critical tasks, and on overall application performance as compared to a conventional LRU cache policy.
BibTeX
@conference{KumVya14A,
title = {Cache Design for Mixed Critical Real-Time Systems},
booktitle = {Proceedings of the International Conference on Computer Design (ICCD)},
year = {2014},
month = oct,
author = {Kumar, Chetan and Vyas, Sudhanshu and Cytron, Ron and Gill, Christopher and Zambreno, Joseph and Jones, Phillip}
}