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Conference Papers
Attia, O., A. Grieve, K. Townsend, P. Jones, and J. Zambreno, "Accelerating All-Pairs Shortest Path Using A Message-Passing Reconfigurable Architecture", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2015. PDF icon AttGri15A.pdf (355.88 KB)
Attia, O., T. Johnson, K. Townsend, P. Jones, and J. Zambreno, "CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2014. PDF icon AttJoh14A.pdf (258.43 KB)
Chen, H., S. Sun, D. Aliprantis, and J. Zambreno, "Dynamic Simulation of DFIG Wind Turbines on FPGA Boards", Proceedings of the Power and Energy Conference at Illinois (PECI), pp. 39-44, February, 2010. PDF icon CheSun10A.pdf (1.49 MB)
Chen, H., S. Sun, D. Aliprantis, and J. Zambreno, "Dynamic Simulation of Electric Machines on FPGA Boards", Proceedings of the International Electric Machines and Drives Conference (IEMDC), May, 2009. PDF icon CheSun09A.pdf (447.25 KB)
Avey, J., P. Jones, and J. Zambreno, "An FPGA-based Hardware Accelerator for Iris Segmentation", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2018. PDF icon AveJon18A.pdf (4.41 MB)
Awatramani, M., J. Zambreno, and D. Rover, "Increasing GPU Throughput using Kernel Interleaved Thread Block Scheduling", Proceedings of the International Conference on Computer Design (ICCD), October, 2013. PDF icon AwaZam13A.pdf (656.95 KB)
Townsend, K., S. Sun, T. Johnson, O. Attia, P. Jones, and J. Zambreno, "k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), May, 2015. PDF icon TowSun15A.pdf (1.03 MB)
Zhu, X., M. Awatramani, D. Rover, and J. Zambreno, "ONAC: Optimal Number of Active Cores Detector for Energy Efficient GPU Computing", Proceedings of the International Conference on Computer Design (ICCD), October, 2016. PDF icon ZhuAwa16A.pdf (820.98 KB)
Awatramani, M., D. Rover, and J. Zambreno, "Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications", Proceedings of the International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems (SRMPDS), September, 2014. PDF icon AwaRov14A.pdf (2.58 MB)
Awatramani, M., X. Zhu, J. Zambreno, and D. Rover, "Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications", Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), October, 2015. PDF icon AwaZhu15A.pdf (3.63 MB)
Journal Articles
Nelson, C., K. Townsend, O. Attia, P. Jones, and J. Zambreno, "RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing", IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, issue 10, 2016. PDF icon NelTow16A.pdf (1.19 MB)
Attia, O., K. Townsend, P. Jones, and J. Zambreno, "A Reconfigurable Architecture for the Detection of Strongly Connected Components", ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 9, issue 2, December, 2015. PDF icon AttTow15A.pdf (1.33 MB)
Townsend, K., O. Attia, P. Jones, and J. Zambreno, "A Scalable Unsegmented Multi-port Memory for FPGA-based Systems", International Journal of Reconfigurable Computing (IJRC), vol. 2015, December, 2015. PDF icon TowAtt16A.pdf (1.44 MB)