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Conference Papers
Attia, O., A. Grieve, K. Townsend, P. Jones, and J. Zambreno, "Accelerating All-Pairs Shortest Path Using A Message-Passing Reconfigurable Architecture", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2015. PDF icon AttGri15A.pdf (355.88 KB)
Attia, O., T. Johnson, K. Townsend, P. Jones, and J. Zambreno, "CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2014. PDF icon AttJoh14A.pdf (258.43 KB)
Townsend, K., P. Jones, and J. Zambreno, "A High Performance Systolic Architecture for k-NN Classification", Proceedings of the International Conference on Formal Methods and Models for Codesign (MEMOCODE), October, 2014. PDF icon TowJon14A.pdf (152.72 KB)
Townsend, K., S. Sun, T. Johnson, O. Attia, P. Jones, and J. Zambreno, "k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), May, 2015. PDF icon TowSun15A.pdf (1.03 MB)
Patterson, M., A. Mills, R. Scheel, J. Tillman, E. Dye, and J. Zambreno, "A Multi-Faceted Approach to FPGA-Based Trojan Circuit Detection", Proceedings of the IEEE VLSI Test Symposium (VTS), April, 2013. PDF icon PatMil13A.pdf (4.38 MB)
Townsend, K., and J. Zambreno, "A Multi-Phase Approach to Floating-Point Compression", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), May, 2015. PDF icon TowZam15A.pdf (215.3 KB)
Monga, M., M. Karkee, L K. Tondehal, B. Steward, A. Kelkar, and J. Zambreno, "Real-Time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform", Proceedings of the International Conference on Computational Science (ICCS), June, 2012. PDF icon MonKar12A.pdf (1.22 MB)
Townsend, K., and J. Zambreno, "Reduce, Reuse, Recycle (R^3): a Design Methodology for Sparse Matrix Vector Multiplication on Reconfigurable Platforms", Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP), June, 2013. PDF icon TowZam13A.pdf (246.79 KB)
Nelson, C., K. Townsend, B S. Rao, P. Jones, and J. Zambreno, "Shepard: A Fast Exact Match Short Read Aligner", Proceedings of the International Conference on Formal Methods and Models for Codesign (MEMOCODE), July, 2012. PDF icon NelTow12A.pdf (134.73 KB)
Journal Articles
Baumgarten, A., A. Tyagi, and J. Zambreno, "Preventing Integrated Circuit Piracy using Reconfigurable Logic Barriers", IEEE Design and Test of Computers, vol. 27, no. 1, pp. 66-75, January, 2010. PDF icon BauTya10A.pdf (730.97 KB)
Nelson, C., K. Townsend, O. Attia, P. Jones, and J. Zambreno, "RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing", IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, issue 10, 2016. PDF icon NelTow16A.pdf (1.19 MB)
Monga, M., D. Roggow, M. Karkee, S. Sun, L K. Tondehal, B. Steward, A. Kelkar, and J. Zambreno, "Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform", Microprocessors and Microsystems, vol. 39, issue 8, pp. 720-740, 2015. PDF icon MonRog15A.pdf (3.21 MB)
Attia, O., K. Townsend, P. Jones, and J. Zambreno, "A Reconfigurable Architecture for the Detection of Strongly Connected Components", ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 9, issue 2, December, 2015. PDF icon AttTow15A.pdf (1.33 MB)
Townsend, K., O. Attia, P. Jones, and J. Zambreno, "A Scalable Unsegmented Multi-port Memory for FPGA-based Systems", International Journal of Reconfigurable Computing (IJRC), vol. 2015, December, 2015. PDF icon TowAtt16A.pdf (1.44 MB)