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Kumar, C., S. Vyas, R. Cytron, C. Gill, J. Zambreno, and P. Jones, "Cache Design for Mixed Critical Real-Time Systems", Proceedings of the International Conference on Computer Design (ICCD), October, 2014. PDF icon KumVya14A.pdf (230.01 KB)
Baumgarten, A., M. Steffen, M. Clausman, and J. Zambreno, "A Case Study in Hardware Trojan Design and Implementation", International Journal of Information Security (IJIS), vol. 10, no. 1, pp. 1-14, 2011. PDF icon BauSte10A.pdf (751.72 KB)
Pande, A., and J. Zambreno, "A Chaotic Encryption Scheme for Real-time Embedded Systems: Design and Implementation", Telecommunication Systems, vol. 52, no. 2, pp. 551-561, 2013. PDF icon PanZam11D.pdf (1.39 MB)
Sayed, M., and P. Jones, "Characterizing Non-Ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-based Thermometers", Proceedings of the International Conference on Reconfigurable Computing and FPGAs (Reconfig), November, 2011. PDF icon SayJon11A.pdf (2.08 MB)
Rilling, J., D. Graziano, J. Hitchcock, T. Meyer, X. Wang, P. Jones, and J. Zambreno, "Circumventing a Ring Oscillator Approach to FPGA-Based Hardware Trojan Detection", Proceedings of the International Conference on Computer Design (ICCD), October, 2011. PDF icon RilGra11A.pdf (203.04 KB)
Pande, A., J. Zambreno, and P. Mohapatra, "Comments on 'Arithmetic Coding as a Non-Linear Dynamical System'", Communications in Nonlinear Science and Numerical Simulation (CNSNS), vol. 17, no. 12, pp. 4536-4543, 2012. PDF icon PanZam12B.pdf (475.31 KB)
Qasaimeh, M., K. Denolf, J. Lo, K. Vissers, J. Zambreno, and P. Jones, "Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels", Proceedings of the IEEE International Conference on Embedded Software and Systems (ICESS), June, 2019. PDF icon QasDen19A.pdf (298.85 KB)
Wang, X., P. Jones, and J. Zambreno, "A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns", Proceedings of the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), June, 2015. PDF icon WanJon15A.pdf (701.98 KB)
Wang, X., P. Jones, and J. Zambreno, "A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns", ACM Computer Architecture News (CAN), vol. 43, issue 4, September, 2015. PDF icon WanJon16A.pdf (1.17 MB)
Attia, O., T. Johnson, K. Townsend, P. Jones, and J. Zambreno, "CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2014. PDF icon AttJoh14A.pdf (258.43 KB)
Saha, S., H. Duwe, and J. Zambreno, "CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks", Journal of Signal Processing Systems, vol. 92, 2020. PDF icon SahDuw20A.pdf (3.98 MB)