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Conference Papers
Zhu, X., R. Wernsman, and J. Zambreno, "Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection", Proceedings of the International Conference on Parallel Processing (ICPP), August, 2018. PDF icon ZhuWer18A.pdf (891.94 KB)
Steffen, M., and J. Zambreno, "Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels", Proceedings of the International Symposium on Microarchitecture (MICRO), pp. 237-248, December, 2010. PDF icon SteZam10B.pdf (529.09 KB)
Kumar, C., S. Vyas, J. Shidal, R. Cytron, C. Gill, J. Zambreno, and P. Jones, "Improving System Predictability and Performance via Hardware Accelerated Data Structures", Proceedings of Dynamic Data Driven Application Systems (DDDAS), June, 2012. PDF icon KumVya12A.pdf (949.92 KB)
Awatramani, M., J. Zambreno, and D. Rover, "Increasing GPU Throughput using Kernel Interleaved Thread Block Scheduling", Proceedings of the International Conference on Computer Design (ICCD), October, 2013. PDF icon AwaZam13A.pdf (656.95 KB)
Steffen, M., P. Jones, and J. Zambreno, "Introducing Graphics Processing from a Systems Perspective: A Hardware / Software Approach", Proceedings of the Annual Conference of the American Society for Engineering Education (ASEE), June, 2012.
Journal Articles
Sun, S., M. Monga, P. Jones, and J. Zambreno, "An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs", IEEE Transactions on Circuits and Systems-I (TCAS-I), vol. 59, no. 1, pp. 113-123, 2012. PDF icon SunMon12A.pdf (840.43 KB)