An Adaptive Property-Aware HW/SW Framework for DDDAS

Support

Air Force Office of Scientific Research (AFOSR) under award FA9550-11-1-0343.

Project Description

This project focuses on the design of an adaptable computing infrastructure to support DDDAS systems in the context of Unmanned Aerial Vehicles (UAVs). A unifying theme that drives our research is the concept of responding and adapting to surprise. Some examples of surprise are: 1) in-flight changes in mission objectives, 2) unexpected encounters with friends or foes, and 3) changes in the environment. Two examples of environmental changes could be a chipped blade (which changes the dynamics of the UAV), or unexpected turbulence.

In support of responding to surprise, research is being pursued to allow elements of the computing platform to adapt to the system or tasks moving between different modalities (e.g. real-time, high-performance, small-footprint, energy-conserving).

Key areas of focus that support adaptation to surprise and changing modalities are:

• Data structures that span HW/SW boundaries: In this area we are exploring SW data structures that can dynamically change their internal makeup to best suite a task’s current modality (e.g. maximizing average throughput when in high-performance mode, or bounding worst-case access time when in a real-time mode), or migrating their storage and operators between SW/HW boundaries to improve performance and/or improve predictability.
• Instruction Set Architecture (ISA) extensions and hardware support: This area focuses on the design and evaluation of specialized hardware to support common tasks that can be found in UAV applications (e.g. sensor acquisition/processing, issuing actuator commands, signal processing, vehicle controller logic) for the purpose of increased computational efficiency (explicitly exploiting concurrency) and/or enforcing guarantees on task behavior (e.g. tightening bounds on execution variation, guarantees on resources availability)
• Establishing performance metrics: i) tolerance of vehicle stability to jitter in its control loop, ii) overheads associated with dynamically morphing data structures or migrating them across SW/HW boundaries.

Project Participants

Investigators

Phillip Jones, Assistant Professor of Electrical Computer and Engineering, PI for this research at Iowa State University.

Joseph Zambreno, Associate Professor of Electrical Computer and Engineering, co-PI for this research at Iowa State University.

Nicola Elia, Professor of Electrical Computer and Engineering, co-PI for this research at Iowa State University.

Ron Cytron, Professor of Computer Science and Engineering, PI for this research at Washington University in St. Louis.

Christopher Gill, Professor of Computer Science and Engineering, is co-PI for this research at Washington University in St. Louis.

Graduate Researchers

Chetan Kumar, Sudhanshu Vyas, John Shidal, and Matt Rich have contributed to this research as graduate Research Assistants

Publications

• C. Kumar, S. Vyas, R. Cytron, C. Gill, J. Zambreno and P. Jones, Cache Design for Mixed Critical Real-Time Systems, Proceedings of the International Conference on Computer Design (ICCD), October, 2014.
• C. Kumar, S. Vyas, R. Cytron, C. Gill, J. Zambreno and P. Jones, Hardware-Software Architecture for Priority Queue Management in Real-time and Embedded Systems, International Journal of Embedded Systems (IJES), vol. 6, no. 4, pp. 319-334, 2014.
• S. Vyas, C. Kumar, J. Zambreno, C. Gill, R. Cytron and P. Jones, An FPGA-based Plant-on-Chip Platform for Cyber-Physical System Analysis, IEEE Embedded Systems Letters (ESL), vol. 6, no. 1, pp. 4-7, 2014.
• C. Kumar, S. Vyas, R. Cytron, C. Gill, J. Zambreno and P. Jones, Scheduling Challenges in Mixed Critical Real-time Heterogeneous Computing Platforms, Proceedings of Dynamic Data Driven Application Systems (DDDAS), June, 2013.
• C. Kumar, S. Vyas, J. Shidal, R. Cytron, C. Gill, J. Zambreno and P. Jones, Improving System Predictability and Performance via Hardware Accelerated Data Structures, Proceedings of Dynamic Data Driven Application Systems (DDDAS) Workshop, June, 2012

Posters

• Chetan Kumar N G, Sudhashu Vyas, Joseph Zambreno and Phillip Jones, Improving System Predictability and Performance via Hardware Accelerated Data Structures, Iowa State University Graduate Student Poster Session, Ames, Iowa, April, 2012.

Presentations

• C. Kumar, S. Vyas, J. Shidal, M. Rich, R. Cytron, C. Gill, J. Zambreno N. Elia, and P. Jones, An Adaptive Property-Aware HW/SW Framework for DDDAS, Dynamic Data Driven Application Systems (DDDAS) PI Meeting, D.C., September, 2013.
• C. Kumar, S. Vyas, M. Rich, R. Cytron, C. Gill, J. Zambreno N. Elia, and P. Jones, Scheduling Challenges in Mixed Critical Heterogeneous Real-Time Computing Platforms, Proceedings of Dynamic Data Driven Application Systems (DDDAS) Workshop, Barcelona, Spain, June, 2013.
• C. Kumar, S. Vyas, J. Shidal, M. Rich, R. Cytron, C. Gill, J. Zambreno N. Elia, and P. Jones, An Adaptive Property-Aware HW/SW Framework for DDDAS, Proceedings of Dynamic Data Driven Application Systems (DDDAS) Workshop, Omaha, NE, June, 2012.