Hardware-Software Architecture for Priority Queue Management in Real-time and Embedded Systems
| Authors | Chetan Kumar, Sudhanshu Vyas, Ron Cytron, Christopher Gill, Joseph Zambreno, and Phillip Jones |
|---|---|
| Type | Journal Article |
| Journal | International Journal of Embedded Systems (IJES) |
| Volume | 6 |
| Issue | 4 |
| Pages | 319-334 |
| Date | 2014 |
Abstract
The use of hardware-based data structures for accelerating real-time and embedded system applications is limited by the scarceness of hardware resources. By their nature, being limited by the silicon area available, hardware data structures cannot scale in size as easily as their software counterparts. We assert a hardware-software co-design approach is required to elegantly overcome these limitations. In this paper, we present a hybrid priority queue architecture that includes a hardware accelerated binary heap that can also be managed in software when its queue size exceeds hardware limits. A memory mapped interface provides software with access to priority-queue-structured on-chip memory, which enables quick and low overhead transitions between hardware and software management. As an application of this hybrid architecture, we present a scalable task scheduler for real-time systems that reduces scheduler processing overhead and improves timing determinism of the scheduler.
BibTeX
@article{KumVya13B,
title = {Hardware-Software Architecture for Priority Queue Management in Real-time and Embedded Systems},
journal = {International Journal of Embedded Systems (IJES)},
volume = {6},
number = {4},
year = {2014},
pages = {319-334},
author = {Kumar, Chetan and Vyas, Sudhanshu and Cytron, Ron and Gill, Christopher and Zambreno, Joseph and Jones, Phillip}
}