|Title||An FPGA Implementation of SipHash|
|Publication Type||Conference Papers|
|Authors||Welte, B., and J. Zambreno|
|Conference Name||Proceedings of the Reconfigurable Architectures Workshop (RAW)|
Cryptographic hash functions play a critical role in ensuring the security and veracity of network transactions; for example, they constitute the backbone of hash-based message authentication codes (HMACs), distributed hash tables (DHTs), and blockchain. However, cryptographic hashing can incur significant CPU overhead, especially for applications that commonly process large inputs exceeding 1 MB. This can make it infeasible to implement HMACs, DHTs, etc. in resource-constrained embedded systems or servers with strict response time requirements. As a solution, we present an FPGA architecture to accelerate SipHash, a promising cryptographic hash function. Our design constitutes the first SipHash implementation that targets maximum performance on an FPGA. The proposed architecture's throughput and acceleration vs. software were measured on Xilinx's Zynq-7000 and Ultrascale+ SoCs for a wide range of input sizes. These results show one core can provide single-threaded throughput of up to 13.7 Gbps on a modern FPGA fabric, and multiple parallel cores can exceed 100 Gbps, allowing applications like blockchain and peer-to-peer file sharing to scale with emerging high-bandwidth networks. A single core can keep pace with 10 Gigabit Ethernet, and further parallelization can empower FPGA designs to fully utilize higher network bandwidths.