Architectures for Simultaneous Coding and Encryption using Chaotic Maps

Title	Architectures for Simultaneous Coding and Encryption using Chaotic Maps
Publication Type	Conference Papers
	2011
Authors	Pande, A., J. Zambreno, and P. Mohapatra
Conference Name	Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Date Published	July
	In this work, we discuss an interpretation of arithmetic coding using chaotic maps. We present a hardware implementation using 64 bit ﬁxed point arithmetic on Virtex-6 FPGA (with and without using DSP slices). The encoder resources are slightly higher than a traditional AC encoder, but there are savings in decoder performance. The architectures achieve clock frequency of 400-500 MHz on Virtex-6 xc6vlx75 device.

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Reconfigurable Computing Laboratory