
@conference {PanZam11B,
	title = {Architectures for Simultaneous Coding and Encryption using Chaotic Maps},
	booktitle = {Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
	year = {2011},
	month = {July},
	abstract = {In this work, we discuss an interpretation of arithmetic coding using chaotic maps. We present a hardware implementation using 64 bit fixed point arithmetic on Virtex-6 FPGA (with and without using DSP slices). The encoder resources are slightly higher than a traditional AC encoder, but there are savings in decoder performance. The architectures achieve clock frequency of 400-500 MHz on Virtex-6 xc6vlx75 device.},
	author = {Amit Pande and Joseph Zambreno and Prasant Mohapatra}
}
