Architectural Support for CPU / GPU Hybridization

Support

National Science Foundation (NSF) under award CCF-1149539.

Project Description

This project investigates the architectural issues inherent in hybrid CPU / GPU designs, in order to remove the limitations on current GPU architectures that limit GPUs to coprocessor status. Specifically, we have set out to accomplish the following five tasks:

Task 1. Provide architectural support for limiting SIMT thread divergence due to complex control flow and non-coalesced memory access. Investigate dynamic thread sorting and warp rescheduling through the use of ISA extensions and custom hardware support.
Task 2. Explore architectural features to enable management threads that will coexist with SIMT computation threads, to allow for efficient dynamic thread creation and suspension, interrupt handling and context switching, and dynamic memory management.
Task 3. Investigate various models of computation in order to design efficient custom computing engines for application regions that limit thread scaling on SIMT-style cores. This task will involve collecting Exascale-relevant benchmarks and isolating significant computational kernels, and in building appropriate HW/SW interfaces to existing SIMT platforms.
Task 4. Investigate security techniques for SIMT-style architectures, to match what is currently available on conventional CPUs. This task will involve designing hardware mechanisms for efficient memory access protection, executable space protection, and strong process isolation.
Task 5. Explore the realm of hardware/software implementation strategies as they pertain to the hybrid CPU / GPU platform innovations, through prototypes on both ends of the realization spectrum, from high-level simulation to FPGA-based emulation.

Project Participants

Investigator

Joseph Zambreno, Professor of Electrical Computer and Engineering, PI for this research at Iowa State University.

Graduate Researchers

Mihir Awatramani, Xian Zhu, Mohammad Pivezhandi, Saunak Saha, Daniel Roggow, Michael Steffen, and Michael Patterson have contributed to this research as graduate Research Assistants

Publications

S. Saha, H. Duwe and J. Zambreno, An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators, Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP), July, 2019.
X. Zhu, R. Wernsman and J. Zambreno, Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection, Proceedings of the International Conference on Parallel Processing (ICPP), August, 2018.
X. Zhu, M. Awatramani, D. Rover and J. Zambreno, ONAC: Optimal Number of Active Cores Detector for Energy Efficient GPU Computing, Proceedings of the International Conference on Computer Design (ICCD), October, 2016.
M. Awatramani, D. Rover and J. Zambreno, Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications, Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), October, 2015.
D. Roggow, P. Uhing, P. Jones and J. Zambreno, A Project-Based Embedded Systems Design Course Using a Reconfigurable SoC Platform, Proceedings of the International Conference on Microelectronic Systems Education (MSE), May, 2015.
M. Awatramani, D. Rover and J. Zambreno, Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications, Proceedings of the International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems (SRMPDS), September, 2014.
M. Awatramani, J. Zambreno and D. Rover, Increasing GPU Throughput using Kernel Interleaved Thread Block Scheduling, Proceedings of the International Conference on Computer Design (ICCD), October, 2013.
M. Steffen, P. Jones and J. Zambreno, Introducing Graphics Processing from a Systems Perspective: A Hardware / Software Approach, Proceedings of the Annual Conference of the American Society for Engineering Education (ASEE), June, 2012.
M. Steffen, P. Jones and J. Zambreno, Teaching Graphics Processing and Architecture using a Hardware Prototyping Approach, Proceedings of the International Conference on Microelectronic Systems Education (MSE), June, 2011.