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Sun, S., M. Monga, P. Jones, and J. Zambreno, "An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs", IEEE Transactions on Circuits and Systems-I (TCAS-I), vol. 59, no. 1, pp. 113-123, 2012. PDF icon SunMon12A.pdf (840.43 KB)
Sun, S., M. Steffen, and J. Zambreno, "A Reconfigurable Platform for Frequent Pattern Mining", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2008. PDF icon SunSte08A.pdf (170.6 KB)
Sun, S., and J. Zambreno, "Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining", IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 22, no. 9, pp. 1497-1505, September, 2011. PDF icon SunZam11A.pdf (916.97 KB)
Sun, S., and J. Zambreno, "Mining Association Rules with Systolic Trees", Proceedings of the International Conference on Field-Programmable Logic and its Applications (FPL), pp. 143-148, September, 2008. PDF icon SunZam08A.pdf (111.29 KB)
Sun, S., J. Yan, and J. Zambreno, "Demonstrable Differential Power Analysis Attacks on Real-World FPGA-Based Embedded Systems", Integrated Computer-Aided Engineering, vol. 16, no. 2, pp. 119-130, April, 2009.
Sun, S., and J. Zambreno, "A Floating-point Accumulator for FPGA-based High Performance Computing Applications", Proceedings of the International Conference on Field-Programmable Technology (FPT), December, 2009. PDF icon SunZam09A.pdf (259.63 KB)
Sun, S., J. Yan, and J. Zambreno, "Experiments in Attacking FPGA-Based Embedded Systems using Differential Power Analysis", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), May, 2008. PDF icon SunYan08A.pdf (177.54 KB)
Steffen, M., P. Jones, and J. Zambreno, "Teaching Graphics Processing and Architecture using a Hardware Prototyping Approach", Proceedings of the International Conference on Microelectronic Systems Education (MSE), June, 2011. PDF icon SteJon11A.pdf (161.26 KB)
Steffen, M., and J. Zambreno, "Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure", Proceedings of Theory and Practice of Computer Graphics (TPCG), June, 2009. PDF icon SteZam09A.pdf (491.13 KB)
Steffen, M., and J. Zambreno, "Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels", Proceedings of the International Symposium on Microarchitecture (MICRO), pp. 237-248, December, 2010. PDF icon SteZam10B.pdf (529.09 KB)
Steffen, M., and J. Zambreno, "A Hardware Pipeline for Accelerating Ray Traversal Algorithms on Streaming Processors", Proceedings of the IEEE Symposium on Application Specific Processors (SASP), June, 2010. PDF icon SteZam10A.pdf (507.46 KB)
Steffen, M., P. Jones, and J. Zambreno, "Introducing Graphics Processing from a Systems Perspective: A Hardware / Software Approach", Proceedings of the Annual Conference of the American Society for Engineering Education (ASEE), June, 2012.
Steffen, M., and J. Zambreno, "Exposing High School Students to Concurrent Programming Principles using Video Game Scripting Engines", Proceedings of the Annual Conference of the American Society for Engineering Education (ASEE), June, 2012.
Sayed, M., and P. Jones, "Characterizing Non-Ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-based Thermometers", Proceedings of the International Conference on Reconfigurable Computing and FPGAs (Reconfig), November, 2011. PDF icon SayJon11A.pdf (2.08 MB)
Sathre, J., and J. Zambreno, "Rollback and Huddle: Architectural Support for Trustworthy Application Replay", Proceedings of the Workshop on Embedded Software Security (WESS), October, 2007. PDF icon SatZam07A.pdf (177.08 KB)
Sathre, J., and J. Zambreno, "Automated Software Attack Recovery using Rollback and Huddle", Springer Journal of Design Automation for Embedded Systems (DAES), vol. 12, no. 3, pp. 243-260, September, 2008. PDF icon SatZam08A.pdf (962.78 KB)
Sathre, J., A. Baumgarten, and J. Zambreno, "Architectural Support for Automated Software Attack Detection, Recovery, and Prevention", Proceedings of the International Conference on Embedded and Ubiquitous Computing (EUC), August, 2009. PDF icon SatBau09A.pdf (279.42 KB)
Saha, S., H. Duwe, and J. Zambreno, "CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks", Journal of Signal Processing Systems, vol. 92, 2020. PDF icon SahDuw20A.pdf (3.98 MB)
Saha, S., H. Duwe, and J. Zambreno, "An Adaptive Memory Management Strategy Towards Energy Efficient Machine Inference in Event-Driven Neuromorphic Accelerators", Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP), July, 2019. PDF icon SahDuwe19A.pdf (900.9 KB)