Export 3 results:
Filters: Author is Xian Zhu  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
I
Zhu, X., R. Wernsman, and J. Zambreno, "Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection", Proceedings of the International Conference on Parallel Processing (ICPP), August, 2018. PDF icon ZhuWer18A.pdf (891.94 KB)
O
Zhu, X., M. Awatramani, D. Rover, and J. Zambreno, "ONAC: Optimal Number of Active Cores Detector for Energy Efficient GPU Computing", Proceedings of the International Conference on Computer Design (ICCD), October, 2016. PDF icon ZhuAwa16A.pdf (820.98 KB)
P
Awatramani, M., X. Zhu, J. Zambreno, and D. Rover, "Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications", Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), October, 2015. PDF icon AwaZhu15A.pdf (3.63 MB)