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2009
Gupte, A., and P. Jones, "Hotspot Mitigation using Dynamic Partial Reconfiguration for Improved Performance", Proceedings of the International Conference on Reconfigurable Computing and FPGAs (Reconfig), December, 2009. PDF icon GupJon09B.pdf (404.56 KB)
Gupte, A., and P. Jones, "Towards Hardware Support for Common Sensor Processing Tasks", Proceedings of the International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), August, 2009. PDF icon GupJon09A.pdf (211.84 KB)
2010
Gupte, A., and P. Jones, "An Evaluation of a Slice Fault Aware Tool Chain", Proceedings of Design, Automation, and Test in Europe (DATE), March, 2010. PDF icon GupJon10A.pdf (644.48 KB)
2011
Sayed, M., and P. Jones, "Characterizing Non-Ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-based Thermometers", Proceedings of the International Conference on Reconfigurable Computing and FPGAs (Reconfig), November, 2011. PDF icon SayJon11A.pdf (2.08 MB)
Rilling, J., D. Graziano, J. Hitchcock, T. Meyer, X. Wang, P. Jones, and J. Zambreno, "Circumventing a Ring Oscillator Approach to FPGA-Based Hardware Trojan Detection", Proceedings of the International Conference on Computer Design (ICCD), October, 2011. PDF icon RilGra11A.pdf (203.04 KB)
Steffen, M., P. Jones, and J. Zambreno, "Teaching Graphics Processing and Architecture using a Hardware Prototyping Approach", Proceedings of the International Conference on Microelectronic Systems Education (MSE), June, 2011. PDF icon SteJon11A.pdf (161.26 KB)
2012
Mills, A., S. Vyas, M. Patterson, C. Sabotta, P. Jones, and J. Zambreno, "Design and Evaluation of a Delay-Based FPGA Physically Unclonable Function", Proceedings of the International Conference on Computer Design (ICCD), September, 2012. PDF icon MilVya12A.pdf (852.76 KB)
Kumar, C., S. Vyas, J. Shidal, R. Cytron, C. Gill, J. Zambreno, and P. Jones, "Improving System Predictability and Performance via Hardware Accelerated Data Structures", Proceedings of Dynamic Data Driven Application Systems (DDDAS), June, 2012. PDF icon KumVya12A.pdf (949.92 KB)
Steffen, M., P. Jones, and J. Zambreno, "Introducing Graphics Processing from a Systems Perspective: A Hardware / Software Approach", Proceedings of the Annual Conference of the American Society for Engineering Education (ASEE), June, 2012.
Sun, S., M. Monga, P. Jones, and J. Zambreno, "An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs", IEEE Transactions on Circuits and Systems-I (TCAS-I), vol. 59, no. 1, pp. 113-123, 2012. PDF icon SunMon12A.pdf (840.43 KB)
Nelson, C., K. Townsend, B S. Rao, P. Jones, and J. Zambreno, "Shepard: A Fast Exact Match Short Read Aligner", Proceedings of the International Conference on Formal Methods and Models for Codesign (MEMOCODE), July, 2012. PDF icon NelTow12A.pdf (134.73 KB)
2013
Vyas, S., A. Gupte, C. Gill, R. Cytron, J. Zambreno, and P. Jones, "Hardware Architectural Support for Control Systems and Sensor Processing", ACM Transactions on Embedded Computing Systems (TECS), vol. 13, no. 2, 2013. PDF icon VyaGup13A.pdf (9.27 MB)
Kumar, C., S. Vyas, R. Cytron, C. Gill, J. Zambreno, and P. Jones, "Scheduling Challenges in Mixed Critical Real-time Heterogeneous Computing Platforms", Proceedings of Dynamic Data Driven Application Systems (DDDAS), June, 2013. PDF icon KumVya13A.pdf (820.8 KB)
2014
Kumar, C., S. Vyas, R. Cytron, C. Gill, J. Zambreno, and P. Jones, "Cache Design for Mixed Critical Real-Time Systems", Proceedings of the International Conference on Computer Design (ICCD), October, 2014. PDF icon KumVya14A.pdf (230.01 KB)
Attia, O., T. Johnson, K. Townsend, P. Jones, and J. Zambreno, "CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2014. PDF icon AttJoh14A.pdf (258.43 KB)
Vyas, S., C. Kumar, J. Zambreno, C. Gill, R. Cytron, and P. Jones, "An FPGA-based Plant-on-Chip Platform for Cyber-Physical System Analysis", IEEE Embedded Systems Letters (ESL), vol. 6, no. 1, pp. 4-7, 2014. PDF icon VyaKum13A.pdf (691.9 KB)
Kumar, C., S. Vyas, R. Cytron, C. Gill, J. Zambreno, and P. Jones, "Hardware-Software Architecture for Priority Queue Management in Real-time and Embedded Systems", International Journal of Embedded Systems (IJES), vol. 6, no. 4, pp. 319-334, 2014. PDF icon KumVya13B.pdf (868.27 KB)
Townsend, K., P. Jones, and J. Zambreno, "A High Performance Systolic Architecture for k-NN Classification", Proceedings of the International Conference on Formal Methods and Models for Codesign (MEMOCODE), October, 2014. PDF icon TowJon14A.pdf (152.72 KB)
Wang, X., P. Jones, and J. Zambreno, "A Reconfigurable Architecture for QR Decomposition Using A Hybrid Approach", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2014. PDF icon WanZam14C.pdf (600.58 KB)
2015
Attia, O., A. Grieve, K. Townsend, P. Jones, and J. Zambreno, "Accelerating All-Pairs Shortest Path Using A Message-Passing Reconfigurable Architecture", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2015. PDF icon AttGri15A.pdf (355.88 KB)
Wang, X., P. Jones, and J. Zambreno, "A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns", Proceedings of the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), June, 2015. PDF icon WanJon15A.pdf (701.98 KB)
Wang, X., P. Jones, and J. Zambreno, "A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns", ACM Computer Architecture News (CAN), vol. 43, issue 4, September, 2015. PDF icon WanJon16A.pdf (1.17 MB)
Gupte, A., S. Vyas, and P. Jones, "A Fault-aware Toolchain Approach for FPGA Fault Tolerance", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 20, no. 2, 2015. PDF icon GupVya15A.pdf (6.71 MB)
Johnson, T., D. Roggow, P. Jones, and J. Zambreno, "An FPGA Architecture for the Recovery of WPA/WPA2 Keys", Journal of Circuits, Systems, and Computers (JCSC), vol. 24, issue 7, 2015. PDF icon JohRog15A.pdf (1.42 MB)
Townsend, K., S. Sun, T. Johnson, O. Attia, P. Jones, and J. Zambreno, "k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), May, 2015. PDF icon TowSun15A.pdf (1.03 MB)
Roggow, D., P. Uhing, P. Jones, and J. Zambreno, "A Project-Based Embedded Systems Design Course Using a Reconfigurable SoC Platform", Proceedings of the International Conference on Microelectronic Systems Education (MSE), May, 2015. PDF icon RogUhi15A.pdf (6.02 MB)
Attia, O., K. Townsend, P. Jones, and J. Zambreno, "A Reconfigurable Architecture for the Detection of Strongly Connected Components", ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 9, issue 2, December, 2015. PDF icon AttTow15A.pdf (1.33 MB)
Townsend, K., O. Attia, P. Jones, and J. Zambreno, "A Scalable Unsegmented Multi-port Memory for FPGA-based Systems", International Journal of Reconfigurable Computing (IJRC), vol. 2015, December, 2015. PDF icon TowAtt16A.pdf (1.44 MB)
Zhang, P., A. Mills, J. Zambreno, and P. Jones, "A Software Configurable and Parallelized Coprocessor Architecture for LQR Control", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2015. PDF icon ZhaMil15A.pdf (1.29 MB)
Mills, A., P. Zhang, S. Vyas, J. Zambreno, and P. Jones, "A Software Configurable Coprocessor-Based State-Space Controller", Proceedings of the International Symposium on Field-Programmable Logic and Applications (FPL), September, 2015. PDF icon MilZha15A.pdf (471.82 KB)
2016
Mills, A., P. Jones, and J. Zambreno, "Parameterizable FPGA-based Kalman Filter Coprocessor Using Piecewise Affine Modeling", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2016. PDF icon MilJon16A.pdf (603.66 KB)
Nelson, C., K. Townsend, O. Attia, P. Jones, and J. Zambreno, "RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing", IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, issue 10, 2016. PDF icon NelTow16A.pdf (1.19 MB)
2017
Zhang, P., A. Mills, J. Zambreno, and P. Jones, "The Design and Integration of a Software Configurable and Parallelized Coprocessor Architecture for LQR Control", Journal of Parallel and Distributed Computing (JPDC), vol. 106, pp. 121-131, 2017. PDF icon ZhaMil17A.pdf (2.06 MB)
Zhang, P., J. Zambreno, and P. Jones, "An Embedded Scalable Linear Model Predictive Hardware-based Controller using ADMM", Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP), July, 2017. PDF icon ZhaZam17A.pdf (2.5 MB)
Qasaimeh, M., P. Jones, and J. Zambreno, "A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2017. PDF icon QasJon17A.pdf (707.38 KB)
2018
Grieve, A., M. Davies, P. Jones, and J. Zambreno, "ARMOR: A Recompilation and Instrumentation-free Monitoring Architecture for Detecting Memory Exploits", IEEE Transactions on Computers (TC), vol. 67, issue 8, 2018. PDF icon GriDav18A.pdf (1.42 MB)
Avey, J., P. Jones, and J. Zambreno, "An FPGA-based Hardware Accelerator for Iris Segmentation", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2018. PDF icon AveJon18A.pdf (4.41 MB)
Cauwels, M., J. Zambreno, and P. Jones, "HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2018. PDF icon CauZam18A.pdf (682.52 KB)
Qasaimeh, M., J. Zambreno, and P. Jones, "A Runtime Configurable Hardware Architecture for Computing Histogram-based Feature Descriptors", Proceedings of the International Symposium on Field-Programmable Logic and Applications (FPL), August, 2018. PDF icon QasZam18A.pdf (661.47 KB)
2019
Qasaimeh, M., K. Denolf, J. Lo, K. Vissers, J. Zambreno, and P. Jones, "Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels", Proceedings of the IEEE International Conference on Embedded Software and Systems (ICESS), June, 2019. PDF icon QasDen19A.pdf (298.85 KB)
2020
Kempa, B., P. Zhang, P. Jones, J. Zambreno, and K Y. Rozier, "Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2", Proceedings of the International Conference on Formal Modeling and Analysis of Timed Systems (FORMATS), September, 2020. PDF icon KemZha20A.pdf (3.11 MB)
Pivezhandi, M., P. Jones, and J. Zambreno, "ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation", Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP), July, 2020. PDF icon PivJon20A.pdf (1.22 MB)
2021
Qasaimeh, M., K. Denolf, A. Khodamoradi, M. Blott, J. Lo, L. Halder, K. Vissers, J. Zambreno, and P. Jones, "Benchmarking Vision Kernels and Neural Network Inference Accelerators on Embedded Platforms", Journal of Systems Architecture, vol. 113, February, 2021. PDF icon QasDen20A.pdf (671.95 KB)
Qasaimeh, M., J. Zambreno, and P. Jones, "An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers", Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP), July, 2021. PDF icon QasZam21A.pdf (1.83 MB)