
@conference {2023,
	title = {An FPGA Implementation of SipHash},
	booktitle = {Proceedings of the Reconfigurable Architectures Workshop (RAW)},
	year = {2023},
	month = {May},
	abstract = {<p>Cryptographic hash functions play a critical role in ensuring the security and veracity of network transactions; for example, they constitute the backbone of hash-based message authentication codes (HMACs), distributed hash tables (DHTs), and blockchain. However, cryptographic hashing can incur significant CPU overhead, especially for applications that commonly process large inputs exceeding 1 MB. This can make it infeasible to implement HMACs, DHTs, etc. in resource-constrained embedded systems or servers with strict response time requirements.\&nbsp; As a solution, we present an FPGA architecture to accelerate SipHash, a promising cryptographic hash function.\&nbsp; Our design constitutes the first SipHash implementation that targets maximum performance on an FPGA. The proposed architecture\&$\#$39;s throughput and acceleration vs. software were measured on Xilinx\&$\#$39;s Zynq-7000 and Ultrascale+ SoCs for a wide range of input sizes.\&nbsp; These results show one core can provide single-threaded throughput of up to 13.7 Gbps on a modern FPGA fabric, and multiple parallel cores can exceed 100 Gbps, allowing applications like blockchain and peer-to-peer file sharing to scale with emerging high-bandwidth networks.\&nbsp; A single core can keep pace with 10 Gigabit Ethernet, and further parallelization can empower FPGA designs to fully utilize higher network bandwidths.</p>
},
	author = {Benjamin Welte and Joseph Zambreno}
}
@article {2021,
	title = {A Fast Markov Decision Process based Algorithm for Collision Avoidance in Urban Air Mobility},
	journal = {IEEE Transactions on Intelligent Transportation Systems (T-ITS)},
	volume = {23},
	year = {2022},
	month = {September},
	abstract = {<div>
	Multiple aircraft collision avoidance is a challenging problem due to a stochastic environment and uncertainty in the intent of other aircraft. Traditionally a layered approach to collision avoidance has been employed using a centralized air traffic control system, established rules of the road, separation assurance, and last minute pairwise collision avoidance. With the advent of Urban Air Mobility (air taxis), the expected increase in traffic density in urban environments, short time scales, and small distances between aircraft favor decentralized decision making on-board the aircraft. In this paper, we present a Markov Decision Process (MDP) based method, named FastMDP, which can solve a certain subclass of MDPs quickly, and demonstrate using the algorithm online to safely maintain separation and avoid collisions with multiple aircraft (1-on-n) while remaining computationally efficient. We compare the FastMDP algorithm\&rsquo;s performance against two online collision avoidance algorithms that have been shown to be both efficient and scale to large numbers of aircraft: Optimal Reciprocal Collision Avoidance (ORCA) and Monte Carlo Tree Search (MCTS). Our simulation results show that under the assumption that aircraft do not have perfect knowledge of other aircraft intent FastMDP outperforms ORCA and MCTS in collision avoidance behavior in terms of loss of separation and near mid-air collisions while being more computationally efficient. We further show that in our simulation FastMDP behaves nearly as well as MCTS with perfect knowledge of other aircraft intent. Our results show that FastMDP is a promising algorithm for collision avoidance that is also computationally efficient.</div>
},
	author = {Joshua Bertram and Peng Wei and Joseph Zambreno}
}
@conference {AveJon18A,
	title = {An FPGA-based Hardware Accelerator for Iris Segmentation},
	booktitle = {Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
	year = {2018},
	month = {December},
	abstract = {Biometric authentication is becoming an increasingly prevalent way to identify a person based on unique physical traits such as their fingerprints, face, and iris. The iris stands out particularly among these traits due to its relative invariability with time and high uniqueness. However, iris recognition without special, dedicated tools like near-infrared (NIR) cameras and stationary high-performance computers is a challenge. Solutions have been proposed to target mobile platforms like smart phones and tablets by making use of the Red-Green-Blue (RGB) camera commonly found on those platforms. These solutions tend to be slower than the former due to the reduced performance available in mobile processors. In this paper, we detail a Field Programmable Gate Array (FPGA)-based System on Chip (SoC) approach to help address the mobility and performance challenges that exist in current iris segmentation solutions. Our SoC architecture allows us to run the iris recognition system in software, while accelerating slower parts of the system by using parallel, dedicated hardware modules. Our approach showed a speedup in segmentation of 22x when compared to an x86-64 platform and 468x when compared to an ARMv7 platform.},
	author = {Joe Avey and Phillip Jones and Joseph Zambreno}
}
@article {GupVya15A,
	title = {A Fault-aware Toolchain Approach for FPGA Fault Tolerance},
	journal = {ACM Transactions on Design Automation of Electronic Systems (TODAES)},
	volume = {20},
	number = {2},
	year = {2015},
	abstract = {As the size and density of silicon chips continue to increase, maintaining acceptable manufacturing yields has become increasingly difficult. Recent works suggest that lithography techniques are reaching their limits with respect to enabling high yield fabrication of small-scale devices, thus there is an increasing need for techniques that can tolerate fabrication time defects. One candidate technology to help combat these defects is reconfigurable hardware. The flexible nature of reconfigurable devices, such as Field Programmable Gate Arrays (FPGAs), makes it possible for them to route around defective areas of a chip after the device has been packaged and deployed into the field.

This work presents a technique that aims to increase the effective yield of FPGA manufacturing by re-claiming a portion of chips that would be ordinarily classified as unusable. In brief, we propose a modification to existing commercial toolchain flows to make them fault aware. A phase is added to identify faults within the chip. The locations of these faults are then used by the toolchain to avoid faults during the placement and routing phase.

Specifically, we have applied our approach to the Xilinx commercial toolchain flow and evaluated its tolerance to both logic and routing resource faults. Our findings show that, at a cost of 5-10\% in device frequency performance, the modified toolchain flow can tolerate up to 30\% of logic resources being faulty and, depending on the nature of the target application, can tolerate 1-30\% of the device{\textquoteright}s routing resources being faulty. These results provide strong evidence that commercial toolchains not designed for the purpose of tolerating faults can still be greatly leveraged in the presence of faults to place and route circuits in an efficient manner.},
	author = {Adwait Gupte and Sudhanshu Vyas and Phillip Jones}
}
@article {JohRog15A,
	title = {An FPGA Architecture for the Recovery of WPA/WPA2 Keys},
	journal = {Journal of Circuits, Systems, and Computers (JCSC)},
	volume = {24},
	year = {2015},
	abstract = {Wi-Fi protected access (WPA) has provided serious improvements over the now deprecated wired equivalent privacy (WEP) protocol. WPA, however, still has some flaws that allow an attacker to obtain the passphrase. One of these flaws is exposed when the access point (AP) is operating in the WPA personal mode. This is the most common mode, as it is the  quickest and easiest to configure. This vulnerability requires the attacker to capture the traffic from the four-way handshake between the AP and client, and then have enough compute time to reverse the passphrase. Increasing the rate at which passphrases can be reversed reduces the amount of time required to construct a repository of service set identifiers (SSIDs) and passphrases, which can increase the chances an attack is successful, or, alternatively, reduce the difficulty of auditing a wireless network for security purposes. This work focuses on creating a Field programmable gate array (FPGA)-based architecture to accelerate the generation of a WPA/WPA2 pairwise master key (PMK) lookup table (LUT) for the recovery of  the passphrase, with special emphasis on the secure hash algorithm-1 (SHA-1) implementation. PMK generation relies heavily on SHA-1 hashing and, as this work shows, an optimized SHA-1 implementation can achieve up to a 40  speedup over an unoptimized implementation when generating PMKs},
	author = {Tyler Johnson and Daniel Roggow and Phillip Jones and Joseph Zambreno}
}
@conference {WanZam14A,
	title = {An FPGA Implementation of the Hestenes-Jacobi Algorithm for Singular Value Decomposition},
	booktitle = {Proceedings of the Reconfigurable Architectures Workshop (RAW)},
	year = {2014},
	month = {May},
	abstract = {As a useful tool for dimensionality reduction, Singular Value Decomposition (SVD) plays an increasingly significant role in many scientific and engineering applications. The high computational complexity of SVD poses challenges for efficient signal processing and data analysis systems, especially for time-sensitive applications with large data sets. While the emergence of FPGAs provides a flexible and low-cost opportunity to pursue high-performance SVD designs, the classical two-sided Jacobi rotation-based SVD architectures are restricted in terms of scalability and input matrix representation. The Hestenes-Jacobi algorithm offers a more parallelizable solution to analyze arbitrary rectangular matrices; however, to date both FPGA and GPU-based implementations have not lived up to the algorithm{\textquoteright}s potential. In this paper, we introduce a floating-point Hestenes-Jacobi architecture for SVD, which is capable of analyzing arbitrary sized matrices. Our implementation on an FPGA-based hybrid acceleration system demonstrates improved efficiency of our architecture compared to an optimized software-based SVD solution for matrices with small to medium column dimensions, even with comparably large row dimensions. The dimensional speedups can be achieved range from 3.8x to 43.6x for matrices with column dimensions from 128 to 256 and row sizes from 128 to 2048. Additionally, we also evaluate the accuracy of our SVD process through convergence analysis.},
	author = {Xinying Wang and Joseph Zambreno}
}
@article {VyaKum13A,
	title = {An FPGA-based Plant-on-Chip Platform for Cyber-Physical System Analysis},
	journal = {IEEE Embedded Systems Letters (ESL)},
	volume = {6},
	number = {1},
	year = {2014},
	pages = {4-7},
	abstract = {Digital control systems are traditionally designed independent of their implementation platform, assuming constant sensor sampling rates and processor response times. Applications are deployed to processors that are shared amongst control and non-control tasks, to maximize resource utilization. This potentially overlooks that computing mechanisms meant for improving average CPU usage, such as cache, interrupts, and task management through schedulers, contribute to non-deterministic interference between tasks. This response time jitter can result in reduced system stability, motivating further study by both the controls and computing communities to maximize CPU utilization, while maintaining physical system stability needs. In this paper, we describe an FPGA-based embedded software platform coupled with a hardware plant emulator (as opposed to purely software-based simulations or hardware-in-the-loop setups) that forms a basis for safe and accurate analysis of Cyber-Physical Systems. We model and analyze an inverted pendulum to demonstrate that our setup can provide a significantly more accurate representation of a real system.},
	author = {Sudhanshu Vyas and Chetan Kumar and Joseph Zambreno and Christopher Gill and Ron Cytron and Phillip Jones}
}
@conference {SunZam09A,
	title = {A Floating-point Accumulator for FPGA-based High Performance Computing Applications},
	booktitle = {Proceedings of the International Conference on Field-Programmable Technology (FPT)},
	year = {2009},
	month = {December},
	abstract = {A floating-point accumulator for FPGA-based high performance computing applications is proposed and evaluated. Compared to previous work, our accumulator uses a fixed size circuit, and can reduce an arbitrary number of input sets of varying sizes without requiring prior knowledge of the bounds of summands. In this paper, we describe how the adder accumulator operator can be heavily pipelined to achieve a high clock speed when mapped to FPGA technology, while still maintaining the original input ordering. Our experimental results show that our accumulator design is very competitive with previous efforts in terms of FPGA resource usage and clock frequency, making it an ideal building block for large-scale sparse matrix computations as implemented in FPGA-based high performance computing systems.},
	author = {Song Sun and Joseph Zambreno}
}
