
@conference {PanZam10A,
	title = {A Reconfigurable Architecture for Secure Multimedia Delivery},
	booktitle = {Proceedings of the International Conference on VLSI Design (VLSID)},
	year = {2010},
	month = {January},
	abstract = {This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the Discrete Wavelet Transform (DWT). This parameterized construction promises multimedia encryption and is also well-suited to a hardware implementation due to our derivation of rational filter coefficients. We achieve an efficient and high-throughput reconfigurable hardware implementation through the use of LUT-based constant multipliers enabling run-time reconfiguration of encryption key. We also compare our prototype (using a Xilinx Virtex 4 FPGA) to several existing implementations in the research literature and show that we achieve superior performance as compared to both traditional CPU-based and custom VLSI approaches while adding features for secure multimedia delivery.},
	author = {Amit Pande and Joseph Zambreno}
}
@article {PanZam10E,
	title = {Reconfigurable Hardware Implementation of a Modified Chaotic Filter Bank Scheme},
	journal = {International Journal of Embedded Systems (IJES)},
	volume = {10},
	number = {3},
	year = {2010},
	pages = {248--258},
	abstract = {Chaotic filter bank schemes have been proposed in the research literature to allow for the efficient encryption of data for real-time embedded systems. Some security flaws have been  found in the underlying approaches which makes such a scheme unsafe for application in real life  scenarios. In this paper, we first present an improved scheme to alleviate the weaknesses of the  chaotic filter bank scheme, and add enhanced security features, to form a modified chaotic filter bank (MCFB) scheme. Next, we present a reconfigurable hardware implementation of the MCFB scheme. Implementation on reconfigurable hardware speeds up the performance of MCFB scheme by mapping some of the multipliers in design to reconfigurable look-up tables, while removing many unnecessary multipliers. An optimised implementation on Xilinx Virtex-5 XC5VLX330 FPGA gave a speedup of 30\% over non-optimised direct implementation. A clock frequency of 88 MHz was obtained. },
	author = {Amit Pande and Joseph Zambreno}
}
