
@book {PanZam13A,
	title = {Embedded Multimedia Security Systems},
	year = {2013},
	pages = {146},
	publisher = {Springer-Verlag},
	organization = {Springer-Verlag},
	address = {London},
	author = {Amit Pande and Joseph Zambreno}
}
@article {PanZam11A,
	title = {Efficient Mapping and Acceleration of AES on Custom Multi-Core Architectures},
	journal = {Concurrency and Computation: Practice and Experience},
	volume = {23},
	number = {4},
	year = {2011},
	pages = {372-389},
	abstract = {Multi-core processors can deliver significant performance benefits for multi-threaded software by adding processing power with minimal latency, given the proximity of the processors. Cryptographic applications are inherently complex and involve large computations. Most cryptographic operations can be translated into logical operations, shift operations, and table look-ups. In this paper we design a novel processor (called -core) with a reconfigurable Arithmetic Logic Unit, and design custom two-dimensional multicore architectures on top of it to accelerate cryptographic kernels. We propose an efficient mapping of instructions from the multi-core grid to the individual processor cores and illustrate the performance of AES-128E algorithm over custom-sized grids. The model was developed using Simulink and the performance analysis suggests a positive trend towards development of large multi-core (or multi--core) architectures to achieve high throughputs in cryptographic operations.},
	author = {Amit Pande and Joseph Zambreno}
}
@conference {PanZam09B,
	title = {An Efficient Hardware Architecture for Multimedia Encryption and Authentication using the Discrete Wavelet Transform},
	booktitle = {Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
	year = {2009},
	month = {May},
	pages = {85-90},
	abstract = {This paper introduces a zero-overhead encryption and authentication scheme for real-time embedded multimedia systems. The parameterized construction of the Discrete Wavelet Transform (DWT) compression block is used to introduce a free parameter in the design. It allows building a keyspace for lightweight multimedia encryption. The parameterization yields rational coefficients leading to an efficient fixed point hardware implementation. A clock speed of over 240 MHz was achieved on a Xilinx Virtex 5 FPGA. Comparison with existing approaches was performed to indicate the high throughput and low hardware overhead in adding the security feature to the DWT architecture.},
	author = {Amit Pande and Joseph Zambreno}
}
@conference {PanZam09C,
	title = {Efficient Translation of Algorithmic Kernels on Large-Scale Multi-Cores},
	booktitle = {Proceedings of the International Workshop on Reconfigurable and Multicore Embedded Systems (WoRMES)},
	year = {2009},
	month = {August},
	abstract = {In this paper we present the design of a novel embedded processor architecture (which we call a {\textmu}-core) that makes use of a reconfigurable ALU. This core serves as the basis of custom 2-dimensional array architectures that can be used to accelerate algorithms such as cryptography and image processing. An efficient translation and mapping of instructions from the multi-core grid to the individual processor cores is proposed and illustrated with an implementation of the AES encryption algorithm on custom-sized grids. A simulation model was developed using Simulink and the performance analysis suggests a positive trend towards the development and utilization of such hardware.},
	author = {Amit Pande and Joseph Zambreno}
}
