
@conference {TowSun15A,
	title = {k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator},
	booktitle = {Proceedings of the IEEE International Conference on Electro/Information Technology (EIT)},
	year = {2015},
	month = {May},
	abstract = {Text classification is an important enabling technology for a wide range of applications such as Internet search, email filtering, network intrusion detection, and data mining electronic documents in general. The k Nearest Neighbors (k-NN) text classification algorithm is among the most accurate classification approaches, but is also among the most computationally expensive. In this paper, we propose accelerating k-NN using a novel reconfigurable hardware based architecture. More specifically, we accelerate a k-NN application{\textquoteright}s core with an FPGA-based sparse matrix vector multiplication coprocessor. On average our implementation shows a speed up factor of 15 over a naive single threaded CPU implementation of k-NN text classification for our datasets, and a speed up factor of 1.5 over a 32-threaded parallelized CPU implementation.},
	author = {Kevin Townsend and Song Sun and Tyler Johnson and Osama Attia and Phillip Jones and Joseph Zambreno}
}
@article {MonRog15A,
	title = {Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform},
	journal = {Microprocessors and Microsystems},
	volume = {39},
	year = {2015},
	pages = {720-740},
	abstract = {With the increase in the complexity of models and lack of flexibility offered by the analog computers, coupled with the advancements in digital hardware, the simulation industry has subsequently moved to digital computers and increased usage of programming languages such as C, C++, and MATLAB. However, the reduced time-step required to simulate complex and fast systems imposes a tighter constraint on the time within which the computations have to be performed. The sequential execution of these computations fails to cope with the real-time constraints which further restrict the usefulness of Real-Time Simulation (RTS) in a Virtual Reality (VR) environment. In this paper, we present a methodology for the design and implementation of RTS algorithms, based on the use of Field-Programmable Gate Array (FPGA) technology. We apply our methodology to an 8th order steering valve subsystem of a vehicle with relatively low response time requirements and use the FPGA technology to improve the response time of this model. Our methodology utilizes traditional hardware/software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator by porting the computationally complex regions to hardware. The hardware design was optimized such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement was made by building a hardware component library of custom accelerators for common non-linear functions. The library also stores the information about resource utilization, cycle count, and the relative error with different bit-width combinations for these components, which is further used to evaluate different partitioning approaches. In this paper, we illustrate the partitioning of a hardware-based simulator design across dual FPGAs, initiate RTS using a system input from a Hardware-in-the-Loop (HIL) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transfer of simulation results back over a socket, shows a speedup of 2x as compared to a similar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design.},
	author = {Madhu Monga and Daniel Roggow and Manoj Karkee and Song Sun and Lakshmi Kiran Tondehal and Brian Steward and Atul Kelkar and Joseph Zambreno}
}
@article {SunMon11A,
	title = {An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs},
	journal = {IEEE Transactions on Circuits and Systems-I (TCAS-I)},
	volume = {59},
	number = {1},
	year = {2012},
	pages = {113-123},
	abstract = {Sparse Matrix-Vector Multiplication (SMVM) is a fundamental core of many high-performance computing applications, including information retrieval, medical imaging, and economic modeling. While the use of reconfigurable computing technology in a high-performance computing environment has shown recent promise in accelerating a wide variety of scientific applications, existing SMVM architectures on FPGA hardware have been limited in that they require either numerous pipeline stalls during computation (due to zero padding) or excessive input preprocessing during run-time. For large-scale sparse matrix scenarios, both of these shortcomings can result in unacceptable performance overheads, limiting the overall value of using FPGAs in a high-performance computing environment. In this paper, we present a scalable and efficient FPGA-based SMVM architecture which can handle arbitrary matrix sparsity patterns without excessive preprocessing or zero padding and can be dynamically expanded based on the available I/O bandwidth. Our experimental results using a commercial FPGA-based acceleration system demonstrate that our reconfigurable SMVM engine is highly efficient, with benchmark-dependent speedups over an optimized software implementation that range from 3.5x to 6.5x in terms of computation time.},
	author = {Song Sun and Madhu Monga and Phillip Jones and Joseph Zambreno}
}
@article {SunZam11A,
	title = {Design and Analysis of a Reconfigurable Platform for Frequent Pattern Mining},
	journal = {IEEE Transactions on Parallel and Distributed Systems (TPDS)},
	volume = {22},
	number = {9},
	year = {2011},
	month = {September},
	pages = {1497-1505},
	abstract = {Frequent pattern mining algorithms are designed to find commonly occurring sets in databases. This class of algorithms is typically very memory intensive, leading to prohibitive runtimes on large databases. A class of reconfigurable architectures has been recently developed that have shown promise in accelerating some data mining applications. In this paper, we propose a new architecture for frequent pattern mining based on a systolic tree structure. The goal of this architecture is to mimic the internal memory layout of the original pattern mining software algorithm while achieving a higher throughput. We provide a detailed analysis of the area and performance requirements of our systolic tree-based architecture, and show that our reconfigurable platform is faster than the original software algorithm for mining long frequent patterns.},
	author = {Song Sun and Joseph Zambreno}
}
@conference {CheSun10A,
	title = {Dynamic Simulation of DFIG Wind Turbines on FPGA Boards},
	booktitle = {Proceedings of the Power and Energy Conference at Illinois (PECI)},
	year = {2010},
	month = {February},
	pages = {39-44},
	abstract = {This paper presents the implementation of a dynamic simulation of a doubly fed induction generator (DFIG)- based wind turbine on a field-programmable gate array (FPGA) board. The explicit fourth-order Runge-Kutta numerical integration algorithm is used to obtain the system dynamic response. The FPGA simulation results and speed improvement are validated versus a Matlab/Simulink simulation. Using FPGAs as computational engines can lead to significant simulation speed gains when compared to a typical PC computer, especially when operations can be efficiently parallelized on the board.},
	author = {Hao Chen and Song Sun and Dionysios Aliprantis and Joseph Zambreno}
}
@article {SunYan09A,
	title = {Demonstrable Differential Power Analysis Attacks on Real-World FPGA-Based Embedded Systems},
	journal = {Integrated Computer-Aided Engineering},
	volume = {16},
	number = {2},
	year = {2009},
	month = {April},
	pages = {119-130},
	abstract = {In the decade since the concept was publicly introduced, power analysis attacks on cryptographic systems have become an increasingly studied topic in the computer security community. Research into countermeasures for these cryptographic systems has intensified as well. Experiments have been conducted showing the potential effectiveness of power analysis attacks and preventative techniques on both software (e.g. smartcard, DSP) and hardware (e.g. ASIC, FPGA) processing elements. One key observation that motivates our work is that the majority of the research into power analysis on FPGA-based cryptographic systems has been a) theoretical in nature, b) evaluated through simulation, or c) experimented using custom hardware that does not closely mirror real-world systems. In this paper, we look to bridge this gap between theory and practice by detailing our experience in performing a Differential Power Analysis (DPA) attack on a commercial FPGA development board. We present an automated data acquisition and analysis design for an FPGA-based implementation of the Data Encryption Standard (DES), and discuss some of the challenges and obstacles that we encountered when performing the DPA attack on our chosen commercial platform.},
	author = {Song Sun and Jackey Yan and Joseph Zambreno}
}
@conference {CheSun09A,
	title = {Dynamic Simulation of Electric Machines on FPGA Boards},
	booktitle = {Proceedings of the International Electric Machines and Drives Conference (IEMDC)},
	year = {2009},
	month = {May},
	abstract = {This paper presents the implementation of an induction machine dynamic simulation on a field-programmable gate array (FPGA) board. Using FPGAs as computational engines can lead to significant simulation speed gains when compared to a typical PC computer, especially when operations can be efficiently parallelized on the board. The textbook example of a free acceleration followed by a step load change is used to outline the basic steps of designing an explicit Runge{\textendash}Kutta numerical ordinary differential equation (ODE) solver on the FPGA platform. The FPGA simulation results and speed improvement are validated versus a Matlab/Simulink simulation.},
	author = {Hao Chen and Song Sun and Dionysios Aliprantis and Joseph Zambreno}
}
@conference {SunZam09A,
	title = {A Floating-point Accumulator for FPGA-based High Performance Computing Applications},
	booktitle = {Proceedings of the International Conference on Field-Programmable Technology (FPT)},
	year = {2009},
	month = {December},
	abstract = {A floating-point accumulator for FPGA-based high performance computing applications is proposed and evaluated. Compared to previous work, our accumulator uses a fixed size circuit, and can reduce an arbitrary number of input sets of varying sizes without requiring prior knowledge of the bounds of summands. In this paper, we describe how the adder accumulator operator can be heavily pipelined to achieve a high clock speed when mapped to FPGA technology, while still maintaining the original input ordering. Our experimental results show that our accumulator design is very competitive with previous efforts in terms of FPGA resource usage and clock frequency, making it an ideal building block for large-scale sparse matrix computations as implemented in FPGA-based high performance computing systems.},
	author = {Song Sun and Joseph Zambreno}
}
@conference {SunYan08A,
	title = {Experiments in Attacking FPGA-Based Embedded Systems using Differential Power Analysis},
	booktitle = {Proceedings of the IEEE International Conference on Electro/Information Technology (EIT)},
	year = {2008},
	month = {May},
	abstract = {In the decade since the concept was publicly introduced, power analysis attacks on cryptographic systems have become an increasingly studied topic in the computer security community. Research into countermeasures for these cryptographic systems has intensified as well. Experiments have been conducted showing the potential effectiveness of power analysis attacks and preventative techniques on both software (e.g. smartcard, DSP) and hardware (e.g. ASIC, FPGA) processing elements. One key observation that motivates our work is that the majority of the research into power analysis on FPGA-based cryptographic systems has been a) theoretical in nature, b) evaluated through simulation, or c) experimented using custom hardware that does not closely mirror real-world systems. In this paper, we look to bridge this gap between theory and practice by detailing our experience in performing a Differential Power Analysis (DPA) attack on a commercial FPGA development board. We present an automated data acquisition and analysis design for an FPGA-based implementation of the Data Encryption Standard (DES), and discuss some of the challenges and obstacles that we encountered when performing the DPA attack on our chosen commercial platform.},
	author = {Song Sun and Jackey Yan and Joseph Zambreno}
}
@conference {SunZam08A,
	title = {Mining Association Rules with Systolic Trees},
	booktitle = {Proceedings of the International Conference on Field-Programmable Logic and its Applications (FPL)},
	year = {2008},
	month = {September},
	pages = {143-148},
	abstract = {Association Rules Mining (ARM) algorithms are designed to find sets of frequently occurring items in large databases. ARM applications have found their way into a variety of fields, including medicine, biotechnology, and marketing. This class of algorithm is typically very memory intensive, leading to prohibitive runtimes on large databases. Previous attempts at acceleration using custom or reconfigurable hardware have been limited, as many of the significant ARM algorithms were designed from a software developer{\textquoteright}s perspective and have features (e.g. dynamic linked lists, recursion) that do not translate well to hardware. In this paper we look at how we can accomplish the goal of association rules mining from a hardware perspective. We investigate a popular tree-based ARM algorithm (FP-growth), and make use of a systolic tree structure, which mimics the internal memory layout of the original software algorithm while achieving much higher throughput. Our experimental prototype demonstrates how we can trade memory resources on a software platform for computational resources on a reconfigurable hardware platform, in order to exploit a fine-grained parallelism that was not inherent in the original ARM algorithm.},
	author = {Song Sun and Joseph Zambreno}
}
@conference {SunSte08A,
	title = {A Reconfigurable Platform for Frequent Pattern Mining},
	booktitle = {Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
	year = {2008},
	month = {December},
	abstract = {In this paper, a new hardware architecture for frequent pattern mining based on a systolic tree structure is proposed. The goal of this architecture is to mimic the internal memory layout of the original FP-growth algorithm while achieving a much higher throughput. We also describe an embedded platform implementation of this architecture along with detailed analysis of area requirements and performance results for different configurations. Our results show that with an appropriate selection of tree size, the reconfigurable platform can be several orders of magnitude faster than the FP-growth algorithm},
	author = {Song Sun and Michael Steffen and Joseph Zambreno}
}
