
@conference {PivJon20A,
	title = {ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation},
	booktitle = {Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
	year = {2020},
	month = {July},
	abstract = {In this paper, we present an FPGA-based architecture for histogram generation to support event-based camera optical flow calculation.  Our proposed histogram generation mechanism reduces memory and logic resources by storing the time difference between consecutive events, instead of the absolute time of each event. Additionally, we explore the trade-off between system resource usage and histogram accuracy as a function of the precision at which time is encoded.  Our results show that across three event-based camera benchmarks we can reduce the encoding of time from 32 to 7 bits with a loss of only approximately 3\% in histogram accuracy.  In comparison to a software implementation, our architecture shows a significant speedup.},
	author = {Mohammad Pivezhandi and Phillip Jones and Joseph Zambreno}
}
@conference {WanZam16A,
	title = {Parallelizing Latent Semantic Indexing Using an FPGA-based Architecture},
	booktitle = {Proceedings of the International Conference on Computer Design (ICCD)},
	year = {2016},
	month = {October},
	abstract = {Latent Semantic Indexing (LSI) has played a significant role in discovering patterns on the relationships between query terms and unstructured documents. However, the inherent characteristics of complex matrix factorization in LSI make it difficult to meet stringent performance requirements. In this paper, we present a deeply pipelined reconfigurable architecture for LSI, which parallelizes the matrix factorization and dimensionality reduction, computation of cosine similarity between vectors, and the ranking of documents. Our architecture implements the reduced Singular Value Decomposition with Hestenes-Jacobi algorithm, in which both singular values and orthogonal vectors are collected, and its components can be reconfigured to update query vector coordinate and calculate query-document similarity. In addition, an ordered tree structure is used to reduce the matrix dimension and rank the documents. Analysis of our design indicates the potential to achieve a performance of 8.9 GFLOPS with dimension-dependent speedups over an optimized software implementation that range from 3.8x to 10.1x in terms of computation time.},
	author = {Xinying Wang and Joseph Zambreno}
}
@conference {MilJon16A,
	title = {Parameterizable FPGA-based Kalman Filter Coprocessor Using Piecewise Affine Modeling},
	booktitle = {Proceedings of the Reconfigurable Architectures Workshop (RAW)},
	year = {2016},
	month = {May},
	abstract = {The Kalman Filter is a robust tool often employed as a plant observer in control systems. However, in the general case the high computational cost, especially for large system models or fast sample rates, makes it an impractical choice for typical low-power microcontrollers. Industry trends towards tighter integration and subsystem consolidation point to the use of powerful high-end SoCs, but this complicates the ability for a controls engineer to verify correct behavior of the system under all conditions, which is important in safety-critical systems.

Dedicated FPGA hardware can provide computational speedup, in addition to firmer design partitioning in mixed-criticality systems and fully deterministic timing, which helps ensure a control system behaves as close as possible to offline simulations. We introduce and compare two variants of a software-configurable FPGA-based implementation of a Kalman Filter. The first is an implementation of an Extended Kalman Filter, while the second is a novel approach{\textendash}the Piecewise-Affine Kalman Filter{\textendash}which may offer significant advantages for certain types of applications.

The state estimate update time and resource requirements are analyzed for plant models up to 28 states. For large models, the designs provide a speedup of 7-12x compared to reference ARM9020T software implementations. An application-agnostic performance analysis demonstrates how the Piecewise-Affine Kalman Filter reduces the software workload and the communication overhead compared to the standard mixed hardware-software Extended Kalman Filter approach.},
	author = {Aaron Mills and Phillip Jones and Joseph Zambreno}
}
@conference {AwaZhu15A,
	title = {Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications},
	booktitle = {Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT)},
	year = {2015},
	month = {October},
	abstract = {Graphics Processing Units (GPUs) have been widely adopted as accelerators for high performance computing due to the immense amount of computational throughput they offer over their CPU counterparts. As GPU architectures are optimized for throughput, they execute a large number of SIMD threads (warps) in parallel and use hardware multithreading to hide the pipeline and memory access latencies. While the Two-Level Round Robin (TLRR) and Greedy Then Oldest (GTO) warp scheduling policies have been widely accepted in the  academic research community, there is no consensus regarding which policy works best for all applications. 

In this paper, we show that the disparity regarding which scheduling policy works better depends on the characteristics of instructions in different regions (phases) of the application. We identify these phases at compile time and design a novel warp scheduling policy that uses information regarding them to make scheduling decisions at runtime. By mitigating the adverse effects of application phase behavior, our policy always performs closer to the better of the two existing policies for each application. We evaluate the performance of the warp schedulers on 35 kernels from the Rodinia and CUDA SDK benchmark suites. For applications that have a better performance with the GTO scheduler, our warp scheduler matches the performance of GTO with 99.2\% accuracy and achieves an average speedup of 6.31\% over RR. Similarly, for applications that perform better with RR, the performance of our scheduler is within of 98\% of RR and achieves an average speedup of 6.65\% over GTO.},
	author = {Mihir Awatramani and Xian Zhu and Joseph Zambreno and Diane Rover}
}
@conference {RogUhi15A,
	title = {A Project-Based Embedded Systems Design Course Using a Reconfigurable SoC Platform},
	booktitle = {Proceedings of the International Conference on Microelectronic Systems Education (MSE)},
	year = {2015},
	month = {May},
	abstract = {Embedded systems are becoming increasingly complex, as typical system components, such as sensors and other specialized processors, are blended together with more traditional microprocessors to form complex systems-on-chips (SoCs). Teaching undergraduate students to understand concepts and technologies behind embedded systems is important in order to prepare these future engineers with the skills and expertise necessary for designing such complex systems. This paper describes an undergraduate course designed to introduce students to embedded system design concepts and challenges in an engaging and effective manner. Our course uses a combination of in-depth laboratory assignments and topical lectures to provide a unique hands-on education for students. Laboratory assignments utilize Avnet{\textquoteright}s ZedBoard platform, a development board built around Xilinx{\textquoteright}s Zynq-7000 SoC, and require students to solve a variety of embedded system challenges from a range of application domains. Overall, student feedback about the course has been positive.},
	author = {Daniel Roggow and Paul Uhing and Phillip Jones and Joseph Zambreno}
}
@conference {AwaRov14A,
	title = {Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications},
	booktitle = {Proceedings of the International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems (SRMPDS)},
	year = {2014},
	month = {September},
	abstract = {Graphic Processing Units (GPUs) achieve latency tolerance by exploiting massive amounts of thread level parallelism. Each core executes several hundred to a few thousand simultaneously active threads. The work scheduler tries to maximize the number of active threads on each core by launching threads until at least one of the required resources is completely utilized. The rationale is, more threads would give the thread scheduler more opportunities to hide memory latency and thus would result in better performance. In this work, we show that launching the maximum number of threads is not always necessary to achieve the best performance. Applications have an optimal thread count value at which the performance saturates. Increasing the number of threads beyond this value results in no better and sometimes worse performance. To this end, we develop Perf-Sat: a mechanism to detect the optimal number of threads required on each core at runtime. Perf-Sat is integrated into the hardware work scheduler and guides it to either increase or decrease the number of active threads. We evaluate the performance impact of our scheduler on two GPU generations and show that Perf-Sat scales well to different applications as well as architectures. With performance loss of less than 1\%, Perf-Sat is able to achieve core resource savings of 18.32\% on average.},
	author = {Mihir Awatramani and Diane Rover and Joseph Zambreno}
}
@conference {KriZam13A,
	title = {Polarity Trend Analysis of Public Sentiment on YouTube},
	booktitle = {Proceedings of the International Conference on Management of Data (COMAD)},
	year = {2013},
	month = {December},
	abstract = {For the past several years YouTube has been by far the largest user-driven online video provider. While many of these videos contain a significant number of user comments, little work has been done to date in extracting trends from these comments because of their low information consistency and quality. In this paper we perform sentiment analysis of the YouTube comments related to popular topics using machine learning techniques. We demonstrate that an analysis of the sentiments to identify their trends, seasonality and forecasts can provide a clear picture of the influence of real-world events on user sentiments.},
	author = {Amar Krishna and Joseph Zambreno and Sandeep Krishnan}
}
@article {PanZam12A,
	title = {Poly-DWT: Polymorphic Wavelet Hardware Support For Dynamic Image Compression},
	journal = {ACM Transactions on Embedded Computing Systems (TECS)},
	volume = {11},
	number = {1},
	year = {2012},
	abstract = {Many modern computing applications have been enabled through the use of real-time multimedia processing. While several hardware architectures have been proposed in the research literature to support such primitives, these fail to address applications whose performance and resource requirements have a dynamic aspect. Embedded multimedia systems typically need a power and computation efficient design in addition to good compression performance. In this paper, we introduce a Polymorphic Wavelet Architecture (Poly-DWT) as a crucial building block towards the development of embedded systems to address such challenges. We illustrate how our Poly-DWT architecture can potentially make dynamic resource allocation decisions, such as the internal bit representation and the processing kernel, according to the application requirements. We introduce a filter switching architecture that allows for dynamic switching between 5/3 and 9/7 wavelet filters and leads to a more power efficient design. Further, a multiplier-free design with a low adder requirement demonstrates the potential of Poly-DWT for embedded systems. Through an FPGA prototype, we perform a quantitative analysis of our Poly-DWT architecture, and compare our filter to existing approaches to illustrate the area and performance benefits inherent in our approach.
},
	author = {Amit Pande and Joseph Zambreno}
}
@article {BauTya10A,
	title = {Preventing Integrated Circuit Piracy using Reconfigurable Logic Barriers},
	journal = {IEEE Design and Test of Computers},
	volume = {27},
	number = {1},
	year = {2010},
	month = {January},
	pages = {66-75},
	abstract = {Hardware metering to prevent IC piracy is a challenging and important problem. The authors propose a combinational locking scheme based on intelligent placement of the barriers throughout the design in which the objective is to maximize the effectiveness of the barriers and to minimize the overhead.},
	author = {Alex Baumgarten and Akhilesh Tyagi and Joseph Zambreno}
}
@conference {PanZam08B,
	title = {Polymorphic Wavelet Architectures using Reconfigurable Hardware},
	booktitle = {Proceedings of the International Conference on Field-Programmable Logic and its Applications (FPL)},
	year = {2008},
	month = {September},
	pages = {471-474},
	abstract = {Traditional microprocessor-based solutions are insufficient to serve the dynamic throughput demands of real-time scalable multimedia processing systems. This paper introduces a Polymorphic Architecture for the Discrete Wavelet Transform (Poly-DWT) as a building block of reconfigurable systems to address these needs. We illustrate how our PolyDWT architecture can dynamically make resource allocation decisions according to application requirements. We perform a quantitative analysis of our Poly-DWT architecture using an FPGA prototype, and compare our filters to existing approaches to illustrate the area and performance benefits inherent in our approach.},
	author = {Amit Pande and Joseph Zambreno}
}
