
@article {SahDuw20A,
	title = {CyNAPSE: A Low-power Reconfigurable Neural Inference Accelerator for Spiking Neural Networks},
	journal = {Journal of Signal Processing Systems},
	volume = {92},
	year = {2020},
	abstract = {While neural network models keep scaling in depth and computational requirements, biologically accurate models are becoming more interesting for low-cost inference. Coupled with the need to bring more computation to the edge in resource-constrained embedded and IoT devices, specialized ultra-low power accelerators for spiking neural networks are being developed. Having a large variance in the models employed in these networks, these accelerators need to be flexible, user-configurable, performant and energy efficient. In this paper, we describe CyNAPSE, a fully digital accelerator designed to emulate neural dynamics of diverse spiking networks. Since the use case of our implementation is primarily concerned with energy efficiency, we take a closer look at the factors that could improve its energy consumption. We observe that while majority of its dynamic power consumption can be credited to memory traffic, its on-chip components suffer greatly from static leakage. Given that the event-driven spike processing algorithm is naturally memory-intensive and has a large number of idle processing elements, it makes sense to tackle each of these problems towards a more efficient hardware implementation. With a diverse set of network benchmarks, we incorporate a detailed study of memory patterns that ultimately informs our choice of an application-specific network-adaptive memory management strategy to reduce dynamic power consumption of the chip. Subsequently, we also propose and evaluate a leakage mitigation
strategy for runtime control of idle power. Using both the RTL implementation and a software simulation of CyNAPSE, we measure the relative benefits of these undertakings. Results show that our adaptive memory management policy results in up to 22\% more reduction in dynamic power consumption.},
	author = {Saunak Saha and Henry Duwe and Joseph Zambreno}
}
@conference {QasDen19A,
	title = {Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels},
	booktitle = {Proceedings of the IEEE International Conference on Embedded Software and Systems (ICESS)},
	year = {2019},
	month = {June},
	abstract = {Developing high performance embedded vision applications requires balancing run-time performance with energy constraints. Given the mix of hardware accelerators that exist for embedded computer vision (e.g. multi-core CPUs, GPUs, and FPGAs), and their associated vendor optimized vision libraries,
it becomes a challenge for developers to navigate this fragmented solution space. To aid with determining which embedded platform is most suitable for their application, we conduct a comprehensive benchmark of the run-time performance and energy efficiency of a wide range of vision kernels. We discuss
rationales for why a given underlying hardware architecture innately performs well or poorly based on the characteristics of a range of vision kernel categories. Specifically, our study is performed for three commonly used HW accelerators for embedded vision applications: ARM57 CPU, Jetson TX2 GPU and ZCU102 FPGA, using their vendor optimized vision libraries: OpenCV, VisionWorks and xfOpenCV. Our results show that the GPU achieves an energy/frame reduction ratio of 1.1{\textendash}3.2X compared to the others for simple kernels. While for more complicated kernels and complete vision pipelines, the FPGA outperforms the others with energy/frame reduction ratios of 1.2{\textendash}22.3X. It is also observed that the FPGA performs increasingly better as a vision application{\textquoteright}s pipeline complexity grows.},
	author = {Murad Qasaimeh and Kristof Denolf and Jack Lo and Kees Vissers and Joseph Zambreno and Phillip Jones}
}
@conference {WanJon15A,
	title = {A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns},
	booktitle = {Proceedings of the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART)},
	year = {2015},
	month = {June},
	abstract = {Sparse LU decomposition has been widely used to solve sparse linear systems of equations found in many scientific and engineering applications, such as circuit simulation, power system modeling and computer vision. However, it is considered a computationally expensive factorization tool. While parallel implementations have been explored to accelerate sparse LU decomposition, irregular sparsity patterns often limit their performance gains. Prior FPGA-based accelerators have been customized to domain-specific sparsity patterns of pre-ordered symmetric matrices. In this paper, we present an efficient architecture for sparse LU decomposition that supports both symmetric and asymmetric sparse matrices with arbitrary sparsity patterns. The control structure of our architecture parallelizes computation and pivoting operations. Also, on-chip resource utilization is configured based on properties of the matrices being processed. Our experimental results show a 1.6 to 14x speedup over an optimized software implementation for benchmarks containing a wide range of sparsity patterns.},
	author = {Xinying Wang and Phillip Jones and Joseph Zambreno}
}
@article {WanJon16A,
	title = {A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns},
	journal = {ACM Computer Architecture News (CAN)},
	volume = {43},
	year = {2015},
	month = {September},
	abstract = {Sparse LU decomposition has been widely used to solve sparse linear systems of equations found in many scientific and engineering applications, such as circuit simulation, power system modeling and computer vision. However, it is considered a computationally expensive factorization tool. While parallel implementations have been explored to accelerate sparse LU decomposition, irregular sparsity patterns often limit their performance gains. Prior FPGA-based accelerators have been customized to domain-specific sparsity patterns of pre-ordered symmetric matrices. In this paper, we present an efficient architecture for sparse LU decomposition that supports both symmetric and asymmetric sparse matrices with arbitrary sparsity patterns. The control structure of our architecture parallelizes computation and pivoting operations. Also, on-chip resource utilization is configured based on properties of the matrices being processed. Our experimental results show a 1.6 to 14x speedup over an optimized software implementation for benchmarks containing a wide range of sparsity patterns.},
	author = {Xinying Wang and Phillip Jones and Joseph Zambreno}
}
@conference {KumVya14A,
	title = {Cache Design for Mixed Critical Real-Time Systems},
	booktitle = {Proceedings of the International Conference on Computer Design (ICCD)},
	year = {2014},
	month = {October},
	abstract = {Shared caches in mixed criticality systems are a source of interference for safety critical tasks. Shared memory not only leads to worst-case execution time (WCET) pessimism, but also affects the response time of safety critical tasks. In this paper, we present a criticality aware cache design which implements a Least Critical (LC) cache replacement policy, where a least recently used non-critical cache line is replaced during a cache miss. The cache acts as a Least Recently Used (LRU) cache if there are no critical lines or if all cache lines are critical in a set. In our design, data within a certain address space is given higher preference in the cache. These critical address spaces are configured using critical address range (CAR) registers. The new cache design was implemented in a Leon3 processor core, a 32bit processor compliant with the SPARC V8 architecture. Experimental results are presented that illustrate the impact of the Least Critical cache replacement policy on the response time of critical tasks, and on overall application performance as compared to a conventional LRU cache policy.},
	author = {Chetan Kumar and Sudhanshu Vyas and Ron Cytron and Christopher Gill and Joseph Zambreno and Phillip Jones}
}
@conference {AttJoh14A,
	title = {CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search},
	booktitle = {Proceedings of the Reconfigurable Architectures Workshop (RAW)},
	year = {2014},
	month = {May},
	abstract = {Large-scale graph structures are considered a keystone for many emerging high-performance computing applications in which Breadth-First Search (BFS) is an important building block. For such graph structures, BFS operations tends to be memory-bound rather than compute-bound. In this paper, we present an efficient reconfigurable architecture for parallel BFS that adopts new optimizations for utilizing memory bandwidth. Our architecture utilizes a custom graph representation based on compressed-sparse raw format (CSR), as well as a restructuring of the conventional BFS algorithm. By taking maximum advantage of available memory bandwidth, our architecture continuously keeps our processing elements active. Using a commercial high-performance reconfigurable computing system (the Convey HC-2), our results demonstrate a 5x speedup over previously published FPGA-based implementations.
},
	author = {Osama Attia and Tyler Johnson and Kevin Townsend and Phillip Jones and Joseph Zambreno}
}
@article {PanZam11D,
	title = {A Chaotic Encryption Scheme for Real-time Embedded Systems: Design and Implementation},
	journal = {Telecommunication Systems},
	volume = {52},
	number = {2},
	year = {2013},
	pages = {551-561},
	abstract = {Chaotic encryption schemes are believed to provide greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details over Xilinx Virtex-6 FPGA are provided. Logistic map is the simplest chaotic system and has high potential to be used to design a stream cipher for real-time embedded systems. Its simple construct and non-linear dynamics makes it a common choice for such applications. In this paper, we present a Modified Logistic Map (MLM) which improves the performance of Logistic Map in terms of higher Lyapunov exponent and uniformity of bifurcation map. It also avoids the stable orbits of logistic map giving a more chaotic behavior to the system. A stream cipher is built using MLM and random feedback scheme. The proposed cipher gives 16 bits of encrypted data per clock cycle. The hardware implementation results over Xilinx Virtex-6 FPGA give a synthesis clock frequency of 93 MHz and a throughput of 1.5 Gbps while using 16 hardware multipliers. This makes the cipher suitable for embedded devices which have tight constraints on power consumption, hardware resources and real-time parameters.},
	author = {Amit Pande and Joseph Zambreno}
}
@article {PanZam12B,
	title = {Comments on {\textquoteright}Arithmetic Coding as a Non-Linear Dynamical System{\textquoteright}},
	journal = {Communications in Nonlinear Science and Numerical Simulation (CNSNS)},
	volume = {17},
	number = {12},
	year = {2012},
	pages = {4536-4543},
	abstract = {Nagaraj et al. [1, 2] present a skewed-non-linear Generalized Luroth Series (s-nGLS) framework. S-nGLS uses non-linear maps for GLS to introduce a security parameter a which is used to build a keyspace for image or data encryption. The map introduces non-linearity to the system to add an "encryption key parameter". The skew is added to achieve optimal compression efficiency. s-nGLS used as such for joint encryption and compression is a weak candidate, as explained in this communication. First, we show how the framework is vulnerable to known plaintext based attacks and that a key of size 256 bits can be broken within 1000 trials. Next, we demonstrate that the proposed non-linearity exponentially increases the hardware complexity of design. We also discover that s-nGlS can{\textquoteright}t be implemented as such for large bitstreams. Finally, we demonstrate how correlation of key  parameter with compression performance leads to further key vulnerabilities.},
	author = {Amit Pande and Joseph Zambreno and Prasant Mohapatra}
}
@article {BauSte10A,
	title = {A Case Study in Hardware Trojan Design and Implementation},
	journal = {International Journal of Information Security (IJIS)},
	volume = {10},
	number = {1},
	year = {2011},
	pages = {1-14},
	abstract = {As integrated circuits (ICs) continue to have an overwhelming presence in our digital information-dominated world, having trust in their manufacture and distribution mechanisms is crucial. However, with ever-shrinking transistor technologies, the cost of new fabrication facilities is becoming prohibitive, pushing industry to make greater use of potentially less reliable foreign sources for their IC supply. The 2008 Computer Security Awareness Week (CSAW) Embedded Systems Challenge at the Polytechnic Institute of NYU highlighted some of the vulnerabilities of the IC supply chain in the form of a hardware hacking challenge. This paper explores the design and implementation of our winning entry.},
	author = {Alex Baumgarten and Michael Steffen and Matthew Clausman and Joseph Zambreno}
}
@conference {RilGra11A,
	title = {Circumventing a Ring Oscillator Approach to FPGA-Based Hardware Trojan Detection},
	booktitle = {Proceedings of the International Conference on Computer Design (ICCD)},
	year = {2011},
	month = {October},
	abstract = {Ring oscillators are commonly used as a locking mechanism that binds a hardware design to a specific area of silicon within an integrated circuit (IC). This locking mechanism can be used to detect malicious modifications to the hardware design, also known as a hardware Trojan, in situations where such modifications result in a change to the physical placement of the design on the IC. However, careful consideration is needed when designing ring oscillators for such a scenario to guarantee the integrity of the locking mechanism. This paper presents a case study in which flaws discovered in a ring oscillator-based Trojan detection scheme allowed for the circumvention of the security mechanism and the implementation of a large and diverse set of hardware Trojans, limited only by hardware resources.},
	author = {Justin Rilling and David Graziano and Jamin Hitchcock and Timothy Meyer and Xinying Wang and Phillip Jones and Joseph Zambreno}
}
