
@conference {SteJon11A,
	title = {Teaching Graphics Processing and Architecture using a Hardware Prototyping Approach},
	booktitle = {Proceedings of the International Conference on Microelectronic Systems Education (MSE)},
	year = {2011},
	month = {June},
	abstract = {Since its introduction over two decades ago, graphics hardware has continued to evolve to improve rendering performance and increase programmability. While most undergraduate courses in computer graphics focus on rendering algorithms and programming APIs, we have recently created an undergraduate senior elective course that focuses on graphics processing and architecture, with a strong emphasis on laboratory work targeting hardware prototyping of the 3D rendering pipeline. In this paper, we present the overall course layout and FPGA-based laboratory infrastructure, that by the end of the semester enables students to implement an OpenGL-compliant graphics processor. To our knowledge, this class is the first that takes a hardware prototyping approach to teaching computer graphics and architecture.},
	author = {Michael Steffen and Phillip Jones and Joseph Zambreno}
}
@conference {GupJon09A,
	title = {Towards Hardware Support for Common Sensor Processing Tasks},
	booktitle = {Proceedings of the International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)},
	year = {2009},
	month = {August},
	abstract = {Sensor processing is a common task within many embedded system domains, such as in control systems sensor feedback used for actuator control, etc. In this paper we have surveyed several embedded system domains, and extracted kernels of computation that are common across applications within a given domain, or across domains. We have shown that adding architectural support for executing these common kernels of computation can yield an overall better system performance. We present a light weight, simplified prototype of a Sensor Processing Unit (SPU) that offloads these computations from the main Arithmetic Logic Unit (ALU) of an embedded processor, and that accesses sensor data in a low latency manner. Our SPU prototype shows an average speed up factor of 2.48 over executing these kernels on an embedded PowerPC processor. A large portion of this speed up is due to our low latency method for accessing sensor data. Isolating our speed up to purely computation still shows an average speed up factor of 1.38 for these kernels.},
	author = {Adwait Gupte and Phillip Jones}
}
