
@article {TowAtt16A,
	title = {A Scalable Unsegmented Multi-port Memory for FPGA-based Systems},
	journal = {International Journal of Reconfigurable Computing (IJRC)},
	volume = {2015},
	year = {2015},
	month = {December},
	abstract = {On-chip multi-port memory cores are crucial primitives for many modern high performance reconfigurable architectures and  multi-core systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage  capacity of the memory. In this paper, we present two approaches for designing multi-port memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multi-port memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.
},
	author = {Kevin Townsend and Osama Attia and Phillip Jones and Joseph Zambreno}
}
@conference {ZhaMil15A,
	title = {A Software Configurable and Parallelized Coprocessor Architecture for LQR Control},
	booktitle = {Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
	year = {2015},
	month = {December},
	abstract = {We present a software configurable and parallelized coprocessor architecture for LQR control that can control physical processes representable by a linear state-space model. Our proposed architecture has distinct advantages over purely software or purely hardware approaches. It differs from other hardware controllers in that it is not hardwired to control one or a small range of plant types (e.g. only electric motors). Via software, an embedded systems engineer can easily reconfigure the controller to suit a wide range of controls applications that can be represented as a state-space model. One goal of our approach is to support a design methodology to help bridge the gap between controls and embedded system software engineering. Control of the well-understood inverted pendulum on a cart is used as an illustrative example of how the proposed hardware accelerator architecture supports our envisioned design methodology for helping bridge this gap. Additionally, we explore the design space of our co-processor{\textquoteright}s parallel architecture in terms of computing speed and resource utilization. Our performance results show a 3.4 to 100 factor speedup over a 666 MHz embedded ARM processor, for plants that can be represented by 4 to 128 states respectively. 
},
	author = {Pei Zhang and Aaron Mills and Joseph Zambreno and Phillip Jones}
}
@conference {MilZha15A,
	title = {A Software Configurable Coprocessor-Based State-Space Controller},
	booktitle = {Proceedings of the International Symposium on Field-Programmable Logic and Applications (FPL)},
	year = {2015},
	month = {September},
	abstract = {We present a software configurable coprocessor-based state-space controller that can control physical processes representable by a linear state-space model.  Our proposed architecture has distinct advantages over purely software or purely hardware approaches. It differs from other hardware controllers in that it is not hardwired to control one or a small range of plant types (e.g. only electric motors). Via software, an embedded systems engineer can easily reconfigure the controller to suit a wide range of controls applications that can be represented as a state-space linear model. Additionally, we introduce a novel design methodology to help bridge the gap between controls and embedded system engineering.  Control of the well-understood inverted pendulum on a cart is used as an illustrative example of how the proposed hardware accelerator architecture supports our envisioned design methodology for helping bridge the gap between controls and embedded software engineering. 
},
	author = {Aaron Mills and Pei Zhang and Sudhanshu Vyas and Joseph Zambreno and Phillip Jones}
}
@conference {KumVya13A,
	title = {Scheduling Challenges in Mixed Critical Real-time Heterogeneous Computing Platforms},
	booktitle = {Proceedings of Dynamic Data Driven Application Systems (DDDAS)},
	year = {2013},
	month = {June},
	abstract = {In Dynamic Data-Driven Application Systems (DDDAS), applications must dynamically adapt their behavior in response to objectives and conditions that change while deployed. Often these applications may be safety critical or tightly resource constrained, with a need for graceful degradation when introduced to unexpected conditions. This paper begins by motivating and providing a vision for a dynamically adaptable mixed critical computing platform to support DDDAS applications. We then specifically focus on the need for advancements in task models and scheduling algorithms to manage the resources of such a platform. We discuss the short comings of existing task models for capturing important attributes of our envisioned computing platform, and identify challenges that must be addressed when developing scheduling algorithms that act upon our proposed extended task model.},
	author = {Chetan Kumar and Sudhanshu Vyas and Ron Cytron and Christopher Gill and Joseph Zambreno and Phillip Jones}
}
@conference {NelTow12A,
	title = {Shepard: A Fast Exact Match Short Read Aligner},
	booktitle = {Proceedings of the International Conference on  Formal Methods and Models for Codesign (MEMOCODE)},
	year = {2012},
	month = {July},
	abstract = {The mapping of many short sequences of DNA, called reads, to a long reference genome is an common task in molecular biology. The task amounts to a simple string search, allowing for a few mismatches due to mutations and inexact read quality. While existing solutions attempt to align a high percentage of the reads using small memory footprints, Shepard is concerned with only exact matches and speed. Using the human genome, Shepard is on the order of hundreds of thousands of times faster than current software  implementations such as SOAP2 or Bowtie, and about 60 times faster than GPU implementations such as SOAP3. 

Shepard contains two components: a software program to preprocess a reference genome into a hash table, and a hardware pipeline for performing fast lookups. The hash table has one entry for each unique 100 base pair sequence that occurs in the reference genome, and contains the index of last occurrence and the number of occurrences. To reduce the hash table size, a minimal perfect hash table is used. The hardware pipeline was designed to perform hash table lookups very quickly, on the order of 600 million lookups per second, and was implemented on a Convey HC-1 high  performance reconfigurable computing system. Shepard streams all of the short reads through a custom hardware pipeline and writes the alignment data (index of last occurrence and number of occurrences) to a binary results array.},
	author = {Chad Nelson and Kevin Townsend and Bhavani Satyanarayana Rao and Phillip Jones and Joseph Zambreno}
}
