
@conference {QasZam18A,
	title = {A Runtime Configurable Hardware Architecture for Computing Histogram-based Feature Descriptors},
	booktitle = {Proceedings of the International Symposium on Field-Programmable Logic and Applications (FPL)},
	year = {2018},
	month = {August},
	abstract = {Feature description is an essential component of many computer vision applications. It encodes the visual contents of images in a manner that is robust against various image transformations. Computing these descriptors is computationally expensive, which causes a performance bottleneck in many embedded vision systems. Although many hardware architectures have been proposed to accelerate feature description computation, most target a single feature description algorithm under specific constraints. The lack of flexibility of such implementations increases development effort if deployed applications need to be modified or upgraded. In this paper, we propose a software configurable hardware architecture capable of computing different types of histogram-based feature descriptors without the need for re-synthesizing the hardware. The architecture takes advantage of data streaming to reduce the computational complexity of computing this class of descriptor. To illustrate the efficiency of our architecture, we deploy two of the most commonly used descriptors (SIFT and HOG) and compare their quality with software implementations. The architecture is also evaluated in terms of execution speed and resource usage and compared with dedicated hardware architectures. Our flexible architecture shows a speed up of 3x and 5x compared to state-of-the-art dedicated hardware architectures for SIFT and HOG, with resource usage overheads [LUTs, FFs, and DSPs] of [1.1x, 15x, and 1.6x] and [6.4x, 7x, and 32x] for SIFT and HOG, respectively.},
	author = {Murad Qasaimeh and Joseph Zambreno and Phillip Jones}
}
@article {NelTow16A,
	title = {RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing},
	journal = {IEEE Transactions on Parallel and Distributed Systems (TPDS)},
	volume = {27},
	year = {2016},
	abstract = {The alignment of many short sequences of DNA, called reads, to a long reference genome is a common task in molecular biology. When the problem is expanded to handle typical workloads of billions of reads, execution time becomes critical. In this paper we present a novel reconfigurable architecture for minimal perfect sequencing (RAMPS). While existing solutions attempt to align a high percentage of the reads using a small memory footprint, RAMPS focuses on performing fast exact matching. Using the human genome as a reference, RAMPS aligns short reads hundreds of thousands of times faster than current software implementations such as SOAP2 or Bowtie, and about a thousand times faster than GPU implementations such as SOAP3.  Whereas other aligners require hours to preprocess reference genomes, RAMPS can preprocess the reference human genome in a few minutes, opening the possibility of using new reference sources that are more genetically similar to the newly sequenced data.},
	author = {Chad Nelson and Kevin Townsend and Osama Attia and Phillip Jones and Joseph Zambreno}
}
@article {AttTow15A,
	title = {A Reconfigurable Architecture for the Detection of Strongly Connected Components},
	journal = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
	volume = {9},
	year = {2015},
	month = {December},
	abstract = {The Strongly Connected Components (SCC) detection algorithm serves as a keystone for many graph analysis applications. The SCC execution time for large-scale graphs, as with many other graph algorithms, is dominated by memory latency. In this paper, we investigate the design of a parallel hardware architecture for the detection of SCCs in directed graphs. We propose a design methodology that alleviates memory latency and problems with irregular memory access. The design is composed of 16 processing elements dedicated to parallel Breadth-First Search (BFS) and 8 processing elements dedicated to finding intersection in parallel. Processing elements are organized to reuse resources and utilize memory bandwidth efficiently. We demonstrate a prototype of our design using the Convey HC-2 system, a commercial high-performance reconfigurable computing coprocessor. Our experimental results show a speedup of as much as 17x for detecting SCCs in large-scale graphs when compared to a conventional sequential software implementation.},
	author = {Osama Attia and Kevin Townsend and Phillip Jones and Joseph Zambreno}
}
@conference {WanZam14C,
	title = {A Reconfigurable Architecture for QR Decomposition Using A Hybrid Approach},
	booktitle = {Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
	year = {2014},
	month = {July},
	abstract = {QR decomposition has been widely used in many signal processing applications to solve linear inverse problems. However, QR decomposition is considered a computationally expensive process, and its sequential implementations fail to meet the requirements of many time-sensitive applications. The Householder transformation and the Givens rotation are the most popular techniques to conduct QR decomposition. Each of these approaches have their own strengths and weakness. The Householder transformation lends itself to efficient sequential implementation, however its inherent data dependencies complicate parallelization. On the other hand, the structure of Givens rotation provides many opportunities for concurrency, but is typically limited by the availability of computing resources. We propose a deeply pipelined reconfigurable architecture that can be dynamically configured to perform either approach in a manner that takes advantage of the strengths of each. At runtime, the input matrix is first partitioned into numerous submatrices. Our architecture then performs parallel Householder  transformations on the sub-matrices in the same column block, which is followed by parallel Givens rotations to annihilate the remaining unneeded individual off-diagonals. Analysis of our design indicates the potential to achieve a performance of 10.5 GFLOPS with speedups of up to 1.46x, 1.15x and 13.75x compared to the MKL implementation, a recent FPGA design and a Matlab solution, respectively.},
	author = {Xinying Wang and Phillip Jones and Joseph Zambreno}
}
