
@conference {ZhuWer18A,
	title = {Improving First Level Cache Efficiency for GPUs Using Dynamic Line Protection},
	booktitle = {Proceedings of the International Conference on Parallel Processing (ICPP)},
	year = {2018},
	month = {August},
	abstract = {
A modern Graphics Processing Unit (GPU) utilizes L1 Data (L1D) caches to reduce memory bandwidth requirements and latencies. However, the L1D cache can easily be overwhelmed by many memory requests from GPU function units, which can bottleneck GPU performance. It has been shown that the performance of L1D caches is greatly reduced for many GPU applications as a large amount of L1D cache lines are replaced before they are re-referenced. By examining the cache access patterns of these applications, we observe L1D caches with low associativity have difficulty capturing data locality for GPU applications with diverse reuse patterns. These patterns result in frequent line replacements and low data re-usage.

To improve the efficiency of L1D caches, we design a Dynamic Line Protection scheme (DLP) that can both preserve valuable cache lines and increase cache line utilization. DLP collects data reuse information from the L1D cache. This information is used to predict protection distances for each memory instruction at runtime, which helps maintain a balance between exploitation of data locality and over-protection of cache lines with long reuse distances. When all cache lines are protected in a set, redundant cache misses are bypassed to reduce the contention for the set. The evaluation result shows that our proposed solution improves cache hits while reducing cache traffic for cache-insufficient applications, achieving up to 137\% and an average of 43\% IPC improvement over the baseline.},
	author = {Xian Zhu and Robert Wernsman and Joseph Zambreno}
}
@conference {ZhuAwa16A,
	title = {ONAC: Optimal Number of Active Cores Detector for Energy Efficient GPU Computing},
	booktitle = {Proceedings of the International Conference on Computer Design (ICCD)},
	year = {2016},
	month = {October},
	abstract = {Graphics Processing Units (GPUs) have become a prevalent platform for high throughput general purpose computing. The peak computational throughput of GPUs has been steadily increasing with each technology node by scaling the number of cores on the chip. Although this vastly improves the performance of several compute-intensive applications, our experiments show that some applications can achieve peak performance without utilizing all cores on the chip. We refer to the number of cores at which performance of an application saturates as the optimal number of active cores (Nopt). We propose executing the application on Nopt cores, and power-gating the unused cores to reduce static power consumption.

Towards this target, we present ONAC (Optimal Number of Active Cores detector), a runtime technique to detect Nopt. ONAC uses a novel estimation model, which significantly reduces the number of hardware samples taken to detect the optimal core count, compared to a sequential detection technique (SeqDet). We implement ONAC and Seq-Det in a cycle-level GPU performance simulator and analyze their effect on performance, power and energy. Our evaluation shows that ONAC and Seq-Det can reduce energy consumption by 20\% and 10\% on average for memory-intensive applications, without sacrificing more than 2\% performance. The higher energy savings for ONAC comes from reducing the detection time by 45\% as compared to Seq-Det.},
	author = {Xian Zhu and Mihir Awatramani and Diane Rover and Joseph Zambreno}
}
@conference {AwaZhu15A,
	title = {Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications},
	booktitle = {Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT)},
	year = {2015},
	month = {October},
	abstract = {Graphics Processing Units (GPUs) have been widely adopted as accelerators for high performance computing due to the immense amount of computational throughput they offer over their CPU counterparts. As GPU architectures are optimized for throughput, they execute a large number of SIMD threads (warps) in parallel and use hardware multithreading to hide the pipeline and memory access latencies. While the Two-Level Round Robin (TLRR) and Greedy Then Oldest (GTO) warp scheduling policies have been widely accepted in the  academic research community, there is no consensus regarding which policy works best for all applications. 

In this paper, we show that the disparity regarding which scheduling policy works better depends on the characteristics of instructions in different regions (phases) of the application. We identify these phases at compile time and design a novel warp scheduling policy that uses information regarding them to make scheduling decisions at runtime. By mitigating the adverse effects of application phase behavior, our policy always performs closer to the better of the two existing policies for each application. We evaluate the performance of the warp schedulers on 35 kernels from the Rodinia and CUDA SDK benchmark suites. For applications that have a better performance with the GTO scheduler, our warp scheduler matches the performance of GTO with 99.2\% accuracy and achieves an average speedup of 6.31\% over RR. Similarly, for applications that perform better with RR, the performance of our scheduler is within of 98\% of RR and achieves an average speedup of 6.65\% over GTO.},
	author = {Mihir Awatramani and Xian Zhu and Joseph Zambreno and Diane Rover}
}
