
@article {NelTow16A,
	title = {RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing},
	journal = {IEEE Transactions on Parallel and Distributed Systems (TPDS)},
	volume = {27},
	year = {2016},
	abstract = {The alignment of many short sequences of DNA, called reads, to a long reference genome is a common task in molecular biology. When the problem is expanded to handle typical workloads of billions of reads, execution time becomes critical. In this paper we present a novel reconfigurable architecture for minimal perfect sequencing (RAMPS). While existing solutions attempt to align a high percentage of the reads using a small memory footprint, RAMPS focuses on performing fast exact matching. Using the human genome as a reference, RAMPS aligns short reads hundreds of thousands of times faster than current software implementations such as SOAP2 or Bowtie, and about a thousand times faster than GPU implementations such as SOAP3.  Whereas other aligners require hours to preprocess reference genomes, RAMPS can preprocess the reference human genome in a few minutes, opening the possibility of using new reference sources that are more genetically similar to the newly sequenced data.},
	author = {Chad Nelson and Kevin Townsend and Osama Attia and Phillip Jones and Joseph Zambreno}
}
@conference {AttGri15A,
	title = {Accelerating All-Pairs Shortest Path Using A Message-Passing Reconfigurable Architecture},
	booktitle = {Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
	year = {2015},
	month = {December},
	abstract = {In this paper, we study the design and implementation of a reconfigurable architecture for graph processing algorithms. The architecture uses a message-passing model targeting shared-memory multi-FPGA platforms. We take advantage of our architecture to showcase a parallel implementation of the all-pairs shortest path algorithm (APSP) for unweighted directed graphs. Our APSP implementation adopts a fine-grain processing methodology while attempting to minimize  communication and synchronization overhead. Our design utilizes 64 parallel kernels for vertex-centric processing. We evaluate a prototype of our system on a Convey HC-2 high performance computing platform, in which our performance results demonstrates an average speedup of 7.9x over the sequential APSP algorithm and an average speedup of 2.38x over a multi-core implementation. 
},
	author = {Osama Attia and Alex Grieve and Kevin Townsend and Phillip Jones and Joseph Zambreno}
}
@conference {TowSun15A,
	title = {k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator},
	booktitle = {Proceedings of the IEEE International Conference on Electro/Information Technology (EIT)},
	year = {2015},
	month = {May},
	abstract = {Text classification is an important enabling technology for a wide range of applications such as Internet search, email filtering, network intrusion detection, and data mining electronic documents in general. The k Nearest Neighbors (k-NN) text classification algorithm is among the most accurate classification approaches, but is also among the most computationally expensive. In this paper, we propose accelerating k-NN using a novel reconfigurable hardware based architecture. More specifically, we accelerate a k-NN application{\textquoteright}s core with an FPGA-based sparse matrix vector multiplication coprocessor. On average our implementation shows a speed up factor of 15 over a naive single threaded CPU implementation of k-NN text classification for our datasets, and a speed up factor of 1.5 over a 32-threaded parallelized CPU implementation.},
	author = {Kevin Townsend and Song Sun and Tyler Johnson and Osama Attia and Phillip Jones and Joseph Zambreno}
}
@conference {TowZam15A,
	title = {A Multi-Phase Approach to Floating-Point Compression},
	booktitle = {Proceedings of the IEEE International Conference on Electro/Information Technology (EIT)},
	year = {2015},
	month = {May},
	abstract = {This paper presents a lossless double-precision floating point compression algorithm. Floating point compression can reduce the cost of storing and transmitting large amounts of data associated with big data problems. A previous algorithm called FPC performs well and uses predictors. However, predictors have limitations. Our program (fzip) overcomes some of these limitations. fzip has 2 phases, first BWT compression, second value and prefix compression with variable length arithmetic encoding. This approach has the advantage that the phases work together and each phase compresses a different type of pattern. On average fzip achieves a 20\% higher compression ratio than other algorithms.},
	author = {Kevin Townsend and Joseph Zambreno}
}
@article {MonRog15A,
	title = {Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform},
	journal = {Microprocessors and Microsystems},
	volume = {39},
	year = {2015},
	pages = {720-740},
	abstract = {With the increase in the complexity of models and lack of flexibility offered by the analog computers, coupled with the advancements in digital hardware, the simulation industry has subsequently moved to digital computers and increased usage of programming languages such as C, C++, and MATLAB. However, the reduced time-step required to simulate complex and fast systems imposes a tighter constraint on the time within which the computations have to be performed. The sequential execution of these computations fails to cope with the real-time constraints which further restrict the usefulness of Real-Time Simulation (RTS) in a Virtual Reality (VR) environment. In this paper, we present a methodology for the design and implementation of RTS algorithms, based on the use of Field-Programmable Gate Array (FPGA) technology. We apply our methodology to an 8th order steering valve subsystem of a vehicle with relatively low response time requirements and use the FPGA technology to improve the response time of this model. Our methodology utilizes traditional hardware/software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator by porting the computationally complex regions to hardware. The hardware design was optimized such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement was made by building a hardware component library of custom accelerators for common non-linear functions. The library also stores the information about resource utilization, cycle count, and the relative error with different bit-width combinations for these components, which is further used to evaluate different partitioning approaches. In this paper, we illustrate the partitioning of a hardware-based simulator design across dual FPGAs, initiate RTS using a system input from a Hardware-in-the-Loop (HIL) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transfer of simulation results back over a socket, shows a speedup of 2x as compared to a similar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design.},
	author = {Madhu Monga and Daniel Roggow and Manoj Karkee and Song Sun and Lakshmi Kiran Tondehal and Brian Steward and Atul Kelkar and Joseph Zambreno}
}
@article {AttTow15A,
	title = {A Reconfigurable Architecture for the Detection of Strongly Connected Components},
	journal = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
	volume = {9},
	year = {2015},
	month = {December},
	abstract = {The Strongly Connected Components (SCC) detection algorithm serves as a keystone for many graph analysis applications. The SCC execution time for large-scale graphs, as with many other graph algorithms, is dominated by memory latency. In this paper, we investigate the design of a parallel hardware architecture for the detection of SCCs in directed graphs. We propose a design methodology that alleviates memory latency and problems with irregular memory access. The design is composed of 16 processing elements dedicated to parallel Breadth-First Search (BFS) and 8 processing elements dedicated to finding intersection in parallel. Processing elements are organized to reuse resources and utilize memory bandwidth efficiently. We demonstrate a prototype of our design using the Convey HC-2 system, a commercial high-performance reconfigurable computing coprocessor. Our experimental results show a speedup of as much as 17x for detecting SCCs in large-scale graphs when compared to a conventional sequential software implementation.},
	author = {Osama Attia and Kevin Townsend and Phillip Jones and Joseph Zambreno}
}
@article {TowAtt16A,
	title = {A Scalable Unsegmented Multi-port Memory for FPGA-based Systems},
	journal = {International Journal of Reconfigurable Computing (IJRC)},
	volume = {2015},
	year = {2015},
	month = {December},
	abstract = {On-chip multi-port memory cores are crucial primitives for many modern high performance reconfigurable architectures and  multi-core systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage  capacity of the memory. In this paper, we present two approaches for designing multi-port memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multi-port memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.
},
	author = {Kevin Townsend and Osama Attia and Phillip Jones and Joseph Zambreno}
}
@conference {AttJoh14A,
	title = {CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search},
	booktitle = {Proceedings of the Reconfigurable Architectures Workshop (RAW)},
	year = {2014},
	month = {May},
	abstract = {Large-scale graph structures are considered a keystone for many emerging high-performance computing applications in which Breadth-First Search (BFS) is an important building block. For such graph structures, BFS operations tends to be memory-bound rather than compute-bound. In this paper, we present an efficient reconfigurable architecture for parallel BFS that adopts new optimizations for utilizing memory bandwidth. Our architecture utilizes a custom graph representation based on compressed-sparse raw format (CSR), as well as a restructuring of the conventional BFS algorithm. By taking maximum advantage of available memory bandwidth, our architecture continuously keeps our processing elements active. Using a commercial high-performance reconfigurable computing system (the Convey HC-2), our results demonstrate a 5x speedup over previously published FPGA-based implementations.
},
	author = {Osama Attia and Tyler Johnson and Kevin Townsend and Phillip Jones and Joseph Zambreno}
}
@conference {TowJon14A,
	title = {A High Performance Systolic Architecture for k-NN Classification},
	booktitle = {Proceedings of the International Conference on Formal Methods and Models for Codesign (MEMOCODE)},
	year = {2014},
	month = {October},
	abstract = {This paper describes the architecture of the winning entry to the 2014 Memocode Design Contest, in the maximum performance category. This year{\textquoteright}s Memocode design contest asks contestants to find the 10 nearest neighbors between 1,000 testing points and 10,000,000 training points. Instead of using Euclidean distance, the contest uses Mahalanobis distance. The contest has 2 awards: the maximum performance award and the cost adjusted performance award.

Our implementation uses a brute force approach that calculates the distance between every testing point to every training point. We use the Convey HC-2ex, a FPGA-based platform. However, the theory applies to software implementations as well. At the time of publication, our runtime is 0.54 seconds.},
	author = {Kevin Townsend and Phillip Jones and Joseph Zambreno}
}
@conference {PatMil13A,
	title = {A Multi-Faceted Approach to FPGA-Based Trojan Circuit Detection},
	booktitle = {Proceedings of the IEEE VLSI Test Symposium (VTS)},
	year = {2013},
	month = {April},
	abstract = {Three general approaches to detecting Trojans embedded in FPGA circuits were explored in the context of the 2012 CSAW Embededed Systems Challenge: functional testing, power analysis, and direct analysis of the bitfile. These tests were used to classify a set of 32 bitfiles which include Trojans of an unknown nature. The project is a step towards developing a framework for Trojan-detection which leverages the strengths of a variety of testing techniques.},
	author = {Michael Patterson and Aaron Mills and Ryan Scheel and Julie Tillman and Evan Dye and Joseph Zambreno}
}
@conference {TowZam13A,
	title = {Reduce, Reuse, Recycle (R^3): a Design Methodology for Sparse Matrix Vector Multiplication on Reconfigurable Platforms},
	booktitle = {Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP)},
	year = {2013},
	month = {June},
	abstract = {Sparse Matrix Vector Multiplication (SpMV) is an important computational kernel in many scientific computing applications. Pipelining multiply-accumulate operations shifts SpMV from a computationally bounded kernel to an I/O bounded kernel. In this paper, we propose a design methodology and hardware architecture for SpMV that seeks to utilize system memory bandwidth as efficiently as possible, by Reducing the matrix element storage with on-chip decompression hardware, Reusing the vector data by mixing row and column matrix traversal, and Recycling data with matrix-dependent on-chip storage. Our experimental results with a Convey HC-1/HC-2 reconfigurable computing system indicate that for certain sparse matrices, our R^3 methodology performs twice as fast as previous reconfigurable implementations, and effectively competes against other platforms.},
	author = {Kevin Townsend and Joseph Zambreno}
}
@conference {MonKar12A,
	title = {Real-Time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform},
	booktitle = {Proceedings of the International Conference on Computational Science (ICCS)},
	year = {2012},
	month = {June},
	abstract = {A purely software-based approach for Real-Time Simulation (RTS) may have difficulties in meeting real-time constraints for complex physical model simulations. In this paper, we present a methodology for the design and implementation of RTS algorithms, based on the use of Field-Programmable Gate Array (FPGA) technology to improve the response time of these models. Our methodology utilizes traditional hardware/software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator. The hardware design was optimized such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement is obtained through the use of custom accelerators for common non-linear functions. Since the systems we examined had relatively low response time requirements, our approach greatly simplifies the software components by porting the computationally complex regions to hardware. We illustrate the partitioning of a hardware-based simulator design across dual FPGAs, initiate RTS using a system input from a Hardware-in-the-Loop (HIL) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transfer of simulation results back over a socket, shows a speedup of 2x as compared to a similar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design.},
	author = {Madhu Monga and Manoj Karkee and Lakshmi Kiran Tondehal and Brian Steward and Atul Kelkar and Joseph Zambreno}
}
@conference {NelTow12A,
	title = {Shepard: A Fast Exact Match Short Read Aligner},
	booktitle = {Proceedings of the International Conference on  Formal Methods and Models for Codesign (MEMOCODE)},
	year = {2012},
	month = {July},
	abstract = {The mapping of many short sequences of DNA, called reads, to a long reference genome is an common task in molecular biology. The task amounts to a simple string search, allowing for a few mismatches due to mutations and inexact read quality. While existing solutions attempt to align a high percentage of the reads using small memory footprints, Shepard is concerned with only exact matches and speed. Using the human genome, Shepard is on the order of hundreds of thousands of times faster than current software  implementations such as SOAP2 or Bowtie, and about 60 times faster than GPU implementations such as SOAP3. 

Shepard contains two components: a software program to preprocess a reference genome into a hash table, and a hardware pipeline for performing fast lookups. The hash table has one entry for each unique 100 base pair sequence that occurs in the reference genome, and contains the index of last occurrence and the number of occurrences. To reduce the hash table size, a minimal perfect hash table is used. The hardware pipeline was designed to perform hash table lookups very quickly, on the order of 600 million lookups per second, and was implemented on a Convey HC-1 high  performance reconfigurable computing system. Shepard streams all of the short reads through a custom hardware pipeline and writes the alignment data (index of last occurrence and number of occurrences) to a binary results array.},
	author = {Chad Nelson and Kevin Townsend and Bhavani Satyanarayana Rao and Phillip Jones and Joseph Zambreno}
}
@article {BauTya10A,
	title = {Preventing Integrated Circuit Piracy using Reconfigurable Logic Barriers},
	journal = {IEEE Design and Test of Computers},
	volume = {27},
	number = {1},
	year = {2010},
	month = {January},
	pages = {66-75},
	abstract = {Hardware metering to prevent IC piracy is a challenging and important problem. The authors propose a combinational locking scheme based on intelligent placement of the barriers throughout the design in which the objective is to maximize the effectiveness of the barriers and to minimize the overhead.},
	author = {Alex Baumgarten and Akhilesh Tyagi and Joseph Zambreno}
}
