
@conference {KemZha20A,
	title = {Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2},
	booktitle = {Proceedings of the International Conference on Formal Modeling and Analysis of Timed Systems (FORMATS)},
	year = {2020},
	month = {September},
	abstract = {Robonaut2 (R2) is a humanoid robot onboard the International Space Station (ISS), performing specialized tasks in collaboration with astronauts. After deployment, R2 developed an unexpected emergent behavior. R2{\textquoteright}s inability to distinguish between knee-joint faults (e.g., due to sensor drift versus violated environmental assumptions) began triggering mid-task, safety-preserving freezes-in-place in the confined space of the ISS, preventing further motion until a ground-control operator determines the root-cause and initiates proper corrective action. Runtime verification (RV) algorithms can efficiently disambiguate the temporal signatures of different faults in real-time. However, no previous RV engine can operate within the limited available resources and specialized platform constraints of R2{\textquoteright}s hardware architecture. An attempt to deploy the only runtime verification engine designed for embedded flight systems, R2U2, failed due to resource constraints. We present a significant redesign of the core R2U2 algorithms to adapt to severe resource and certification constraints and prove their correctness, time complexity, and space requirements. We further define optimizations enabled by our new algorithms and implement the new version of R2U2. We encode specifications describing real-life faults occurring onboard Robonaut2 using MLTL and detail our process of specification debugging, validation, and refinement. We deploy this new version of R2U2 on Robonaut2, demonstrating successful real-time fault disambiguation and mitigation triggering of R2{\textquoteright}s knee-joint faults without false positives.},
	author = {Brian Kempa and Pei Zhang and Phillip Jones and Joseph Zambreno and Kristin Yvonne Rozier}
}
@conference {OluEze19A,
	title = {Anomaly Detection Approach Using Adaptive Cumulative Sum Algorithm for Controller Area Network},
	booktitle = {Proceedings of the ACM Workshop on Automotive Cybersecurity (AutoSec)},
	year = {2019},
	month = {March},
	abstract = {The modern vehicle has transformed from a purely mechanical system to a system that embeds several electronic devices. These devices communicate through the in-vehicle network for enhanced safety and comfort but are vulnerable to cyber-physical risks and attacks. A well-known technique of detecting these attacks and unusual events is by using intrusion detection systems. Anomalies in the network occur at unknown points and produce abrupt changes in the statistical features of the message stream. In this paper, we propose an anomaly-based intrusion detection approach using the cumulative sum (CUSUM) change-point detection algorithm to detect data injection attacks on the controller area network (CAN) bus. We leverage the parameters required for the change-point algorithm to reduce false alarm rate and detection delay. Using real dataset generated from a car in normal operation, we evaluate our detection approach on three different kinds of attack scenarios.},
	author = {Habeeb Olufowobi and Uchenna Ezeobi and Eric Muhati and Gaylon Robinson and Clinton Young and Joseph Zambreno and Gedare Bloom}
}
@conference {ZhuAwa16A,
	title = {ONAC: Optimal Number of Active Cores Detector for Energy Efficient GPU Computing},
	booktitle = {Proceedings of the International Conference on Computer Design (ICCD)},
	year = {2016},
	month = {October},
	abstract = {Graphics Processing Units (GPUs) have become a prevalent platform for high throughput general purpose computing. The peak computational throughput of GPUs has been steadily increasing with each technology node by scaling the number of cores on the chip. Although this vastly improves the performance of several compute-intensive applications, our experiments show that some applications can achieve peak performance without utilizing all cores on the chip. We refer to the number of cores at which performance of an application saturates as the optimal number of active cores (Nopt). We propose executing the application on Nopt cores, and power-gating the unused cores to reduce static power consumption.

Towards this target, we present ONAC (Optimal Number of Active Cores detector), a runtime technique to detect Nopt. ONAC uses a novel estimation model, which significantly reduces the number of hardware samples taken to detect the optimal core count, compared to a sequential detection technique (SeqDet). We implement ONAC and Seq-Det in a cycle-level GPU performance simulator and analyze their effect on performance, power and energy. Our evaluation shows that ONAC and Seq-Det can reduce energy consumption by 20\% and 10\% on average for memory-intensive applications, without sacrificing more than 2\% performance. The higher energy savings for ONAC comes from reducing the detection time by 45\% as compared to Seq-Det.},
	author = {Xian Zhu and Mihir Awatramani and Diane Rover and Joseph Zambreno}
}
@article {JohRog15A,
	title = {An FPGA Architecture for the Recovery of WPA/WPA2 Keys},
	journal = {Journal of Circuits, Systems, and Computers (JCSC)},
	volume = {24},
	year = {2015},
	abstract = {Wi-Fi protected access (WPA) has provided serious improvements over the now deprecated wired equivalent privacy (WEP) protocol. WPA, however, still has some flaws that allow an attacker to obtain the passphrase. One of these flaws is exposed when the access point (AP) is operating in the WPA personal mode. This is the most common mode, as it is the  quickest and easiest to configure. This vulnerability requires the attacker to capture the traffic from the four-way handshake between the AP and client, and then have enough compute time to reverse the passphrase. Increasing the rate at which passphrases can be reversed reduces the amount of time required to construct a repository of service set identifiers (SSIDs) and passphrases, which can increase the chances an attack is successful, or, alternatively, reduce the difficulty of auditing a wireless network for security purposes. This work focuses on creating a Field programmable gate array (FPGA)-based architecture to accelerate the generation of a WPA/WPA2 pairwise master key (PMK) lookup table (LUT) for the recovery of  the passphrase, with special emphasis on the secure hash algorithm-1 (SHA-1) implementation. PMK generation relies heavily on SHA-1 hashing and, as this work shows, an optimized SHA-1 implementation can achieve up to a 40  speedup over an unoptimized implementation when generating PMKs},
	author = {Tyler Johnson and Daniel Roggow and Phillip Jones and Joseph Zambreno}
}
@conference {AwaZhu15A,
	title = {Phase Aware Warp Scheduling: Mitigating Effects of Phase Behavior in GPGPU Applications},
	booktitle = {Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT)},
	year = {2015},
	month = {October},
	abstract = {Graphics Processing Units (GPUs) have been widely adopted as accelerators for high performance computing due to the immense amount of computational throughput they offer over their CPU counterparts. As GPU architectures are optimized for throughput, they execute a large number of SIMD threads (warps) in parallel and use hardware multithreading to hide the pipeline and memory access latencies. While the Two-Level Round Robin (TLRR) and Greedy Then Oldest (GTO) warp scheduling policies have been widely accepted in the  academic research community, there is no consensus regarding which policy works best for all applications. 

In this paper, we show that the disparity regarding which scheduling policy works better depends on the characteristics of instructions in different regions (phases) of the application. We identify these phases at compile time and design a novel warp scheduling policy that uses information regarding them to make scheduling decisions at runtime. By mitigating the adverse effects of application phase behavior, our policy always performs closer to the better of the two existing policies for each application. We evaluate the performance of the warp schedulers on 35 kernels from the Rodinia and CUDA SDK benchmark suites. For applications that have a better performance with the GTO scheduler, our warp scheduler matches the performance of GTO with 99.2\% accuracy and achieves an average speedup of 6.31\% over RR. Similarly, for applications that perform better with RR, the performance of our scheduler is within of 98\% of RR and achieves an average speedup of 6.65\% over GTO.},
	author = {Mihir Awatramani and Xian Zhu and Joseph Zambreno and Diane Rover}
}
@conference {RogUhi15A,
	title = {A Project-Based Embedded Systems Design Course Using a Reconfigurable SoC Platform},
	booktitle = {Proceedings of the International Conference on Microelectronic Systems Education (MSE)},
	year = {2015},
	month = {May},
	abstract = {Embedded systems are becoming increasingly complex, as typical system components, such as sensors and other specialized processors, are blended together with more traditional microprocessors to form complex systems-on-chips (SoCs). Teaching undergraduate students to understand concepts and technologies behind embedded systems is important in order to prepare these future engineers with the skills and expertise necessary for designing such complex systems. This paper describes an undergraduate course designed to introduce students to embedded system design concepts and challenges in an engaging and effective manner. Our course uses a combination of in-depth laboratory assignments and topical lectures to provide a unique hands-on education for students. Laboratory assignments utilize Avnet{\textquoteright}s ZedBoard platform, a development board built around Xilinx{\textquoteright}s Zynq-7000 SoC, and require students to solve a variety of embedded system challenges from a range of application domains. Overall, student feedback about the course has been positive.},
	author = {Daniel Roggow and Paul Uhing and Phillip Jones and Joseph Zambreno}
}
@article {MonRog15A,
	title = {Real-time Simulation of Dynamic Vehicle Models using a High-performance Reconfigurable Platform},
	journal = {Microprocessors and Microsystems},
	volume = {39},
	year = {2015},
	pages = {720-740},
	abstract = {With the increase in the complexity of models and lack of flexibility offered by the analog computers, coupled with the advancements in digital hardware, the simulation industry has subsequently moved to digital computers and increased usage of programming languages such as C, C++, and MATLAB. However, the reduced time-step required to simulate complex and fast systems imposes a tighter constraint on the time within which the computations have to be performed. The sequential execution of these computations fails to cope with the real-time constraints which further restrict the usefulness of Real-Time Simulation (RTS) in a Virtual Reality (VR) environment. In this paper, we present a methodology for the design and implementation of RTS algorithms, based on the use of Field-Programmable Gate Array (FPGA) technology. We apply our methodology to an 8th order steering valve subsystem of a vehicle with relatively low response time requirements and use the FPGA technology to improve the response time of this model. Our methodology utilizes traditional hardware/software co-design approaches to generate a heterogeneous architecture for an FPGA-based simulator by porting the computationally complex regions to hardware. The hardware design was optimized such that it efficiently utilizes the parallel nature of FPGAs and pipelines the independent operations. Further enhancement was made by building a hardware component library of custom accelerators for common non-linear functions. The library also stores the information about resource utilization, cycle count, and the relative error with different bit-width combinations for these components, which is further used to evaluate different partitioning approaches. In this paper, we illustrate the partitioning of a hardware-based simulator design across dual FPGAs, initiate RTS using a system input from a Hardware-in-the-Loop (HIL) framework, and use these simulation results from our FPGA-based platform to perform response analysis. The total simulation time, which includes the time required to receive the system input over a socket (without HIL), software initialization, hardware computation, and transfer of simulation results back over a socket, shows a speedup of 2x as compared to a similar setup with no hardware acceleration. The correctness of the simulation output from the hardware has also been validated with the simulated results from the software-only design.},
	author = {Madhu Monga and Daniel Roggow and Manoj Karkee and Song Sun and Lakshmi Kiran Tondehal and Brian Steward and Atul Kelkar and Joseph Zambreno}
}
@conference {AwaRov14A,
	title = {Perf-Sat: Runtime Detection of Performance Saturation for GPGPU Applications},
	booktitle = {Proceedings of the International Workshop on Scheduling and Resource Management for Parallel and Distributed Systems (SRMPDS)},
	year = {2014},
	month = {September},
	abstract = {Graphic Processing Units (GPUs) achieve latency tolerance by exploiting massive amounts of thread level parallelism. Each core executes several hundred to a few thousand simultaneously active threads. The work scheduler tries to maximize the number of active threads on each core by launching threads until at least one of the required resources is completely utilized. The rationale is, more threads would give the thread scheduler more opportunities to hide memory latency and thus would result in better performance. In this work, we show that launching the maximum number of threads is not always necessary to achieve the best performance. Applications have an optimal thread count value at which the performance saturates. Increasing the number of threads beyond this value results in no better and sometimes worse performance. To this end, we develop Perf-Sat: a mechanism to detect the optimal number of threads required on each core at runtime. Perf-Sat is integrated into the hardware work scheduler and guides it to either increase or decrease the number of active threads. We evaluate the performance impact of our scheduler on two GPU generations and show that Perf-Sat scales well to different applications as well as architectures. With performance loss of less than 1\%, Perf-Sat is able to achieve core resource savings of 18.32\% on average.},
	author = {Mihir Awatramani and Diane Rover and Joseph Zambreno}
}
@conference {MihZam13A,
	title = {Increasing GPU Throughput using Kernel Interleaved Thread Block Scheduling},
	booktitle = {Proceedings of the International Conference on Computer Design (ICCD)},
	year = {2013},
	month = {October},
	abstract = {The number of active threads required to achieve peak application throughput on graphics processing units (GPUs) depends largely on the ratio of time spent on computation to the time spent accessing data from memory. While compute-intensive applications can achieve peak throughput with a low number of threads, memory-intensive applications might not achieve good throughput even at the maximum supported thread count. In this paper, we study the effects of scheduling work from multiple applications on the same GPU core. We claim that interleaving workload from different applications on a GPU core can improve the utilization of computational units and reduce the load on memory subsystem. Experiments on 17 application pairs from the Rodinia benchmark suite show that overall throughput increases by 7\% on average.},
	author = {Mihir Awatramani and Joseph Zambreno and Diane Rover}
}
@conference {NelTow12A,
	title = {Shepard: A Fast Exact Match Short Read Aligner},
	booktitle = {Proceedings of the International Conference on  Formal Methods and Models for Codesign (MEMOCODE)},
	year = {2012},
	month = {July},
	abstract = {The mapping of many short sequences of DNA, called reads, to a long reference genome is an common task in molecular biology. The task amounts to a simple string search, allowing for a few mismatches due to mutations and inexact read quality. While existing solutions attempt to align a high percentage of the reads using small memory footprints, Shepard is concerned with only exact matches and speed. Using the human genome, Shepard is on the order of hundreds of thousands of times faster than current software  implementations such as SOAP2 or Bowtie, and about 60 times faster than GPU implementations such as SOAP3. 

Shepard contains two components: a software program to preprocess a reference genome into a hash table, and a hardware pipeline for performing fast lookups. The hash table has one entry for each unique 100 base pair sequence that occurs in the reference genome, and contains the index of last occurrence and the number of occurrences. To reduce the hash table size, a minimal perfect hash table is used. The hardware pipeline was designed to perform hash table lookups very quickly, on the order of 600 million lookups per second, and was implemented on a Convey HC-1 high  performance reconfigurable computing system. Shepard streams all of the short reads through a custom hardware pipeline and writes the alignment data (index of last occurrence and number of occurrences) to a binary results array.},
	author = {Chad Nelson and Kevin Townsend and Bhavani Satyanarayana Rao and Phillip Jones and Joseph Zambreno}
}
@conference {RilGra11A,
	title = {Circumventing a Ring Oscillator Approach to FPGA-Based Hardware Trojan Detection},
	booktitle = {Proceedings of the International Conference on Computer Design (ICCD)},
	year = {2011},
	month = {October},
	abstract = {Ring oscillators are commonly used as a locking mechanism that binds a hardware design to a specific area of silicon within an integrated circuit (IC). This locking mechanism can be used to detect malicious modifications to the hardware design, also known as a hardware Trojan, in situations where such modifications result in a change to the physical placement of the design on the IC. However, careful consideration is needed when designing ring oscillators for such a scenario to guarantee the integrity of the locking mechanism. This paper presents a case study in which flaws discovered in a ring oscillator-based Trojan detection scheme allowed for the circumvention of the security mechanism and the implementation of a large and diverse set of hardware Trojans, limited only by hardware resources.},
	author = {Justin Rilling and David Graziano and Jamin Hitchcock and Timothy Meyer and Xinying Wang and Phillip Jones and Joseph Zambreno}
}
