
@article {PanChe13A,
	title = {Hardware Architecture for Video Authentication using Sensor Pattern Noise},
	journal = {IEEE Transactions on Circuits and Systems for Video Technology (TCSVT)},
	volume = {24},
	number = {1},
	year = {2014},
	pages = {157-167},
	abstract = {Digital camera identification can be accomplished based on sensor pattern noise which is unique to a device and serves as a distinct identification fingerprint. Camera identification and authentication has formed the basis of image / video forensics in legal proceedings. Unfortunately, real-time video source identification is a computationally heavy task, and does not scale well to conventional software implementations on typical embedded devices. In this paper, we propose a hardware architecture for source identification in networked cameras. The underlying algorithms, an orthogonal forward and inverse Discrete Wavelet Transform (DWT) and Minimum Mean Square Error (MMSE) based Estimation have been optimized for 2D frame sequences in terms of area and throughput performance. We exploit parallelism, pipelining and hardware reuse techniques to minimize hardware resource utilization and increase the achievable throughput of the design. A prototype implementation on a Xilinx Virtex-6 FPGA device was optimized with a resulting throughput of 167 MBps, processing 30 640 {\texttimes} 480 video frames in 0.17 second.},
	author = {Amit Pande and Shaxun Chen and Prasant Mohapatra and Joseph Zambreno}
}
@article {PanZam11D,
	title = {A Chaotic Encryption Scheme for Real-time Embedded Systems: Design and Implementation},
	journal = {Telecommunication Systems},
	volume = {52},
	number = {2},
	year = {2013},
	pages = {551-561},
	abstract = {Chaotic encryption schemes are believed to provide greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details over Xilinx Virtex-6 FPGA are provided. Logistic map is the simplest chaotic system and has high potential to be used to design a stream cipher for real-time embedded systems. Its simple construct and non-linear dynamics makes it a common choice for such applications. In this paper, we present a Modified Logistic Map (MLM) which improves the performance of Logistic Map in terms of higher Lyapunov exponent and uniformity of bifurcation map. It also avoids the stable orbits of logistic map giving a more chaotic behavior to the system. A stream cipher is built using MLM and random feedback scheme. The proposed cipher gives 16 bits of encrypted data per clock cycle. The hardware implementation results over Xilinx Virtex-6 FPGA give a synthesis clock frequency of 93 MHz and a throughput of 1.5 Gbps while using 16 hardware multipliers. This makes the cipher suitable for embedded devices which have tight constraints on power consumption, hardware resources and real-time parameters.},
	author = {Amit Pande and Joseph Zambreno}
}
@book {PanZam13A,
	title = {Embedded Multimedia Security Systems},
	year = {2013},
	pages = {146},
	publisher = {Springer-Verlag},
	organization = {Springer-Verlag},
	address = {London},
	author = {Amit Pande and Joseph Zambreno}
}
@article {PanMoh12A,
	title = {Securing Multimedia Content using Joint Compression and Encryption},
	journal = {IEEE MultiMedia},
	volume = {20},
	number = {4},
	year = {2013},
	pages = {50-61},
	abstract = {Algorithmic parameterization and hardware architectures can ensure secure transmission of multimedia data in resource-constrained environments such as wireless video surveillance networks, tele-medicine frameworks for distant health care support in rural areas, and Internet video streaming.

Joint multimedia compression and encryption techniques can significantly reduce the computational requirements of video processing systems. We present an approach to reduce the computational cost of multimedia encryption, while also preserving the properties of compressed video (useful for scalability, transcoding, and retrieval), which endanger loss by naive encryption. Hardware-amenable design of proposed algorithms makes them suitable for real-time embedded multimedia systems. This approach alleviates the need of additional hardware for encryption in resource constrained scenario, and can be otherwise used to augment existing encryption methods used for content delivery in Internet or other applications.

In this work, we show how two compression blocks for video coding: a modified frequency transform (called as Secure Wavelet Transform or SWT) and a modified entropy coding scheme, (called Chaotic Arithmetic Coding (CAC)) can be used for video encryption. Experimental results are shown for selective encryption using proposed schemes.

},
	author = {Amit Pande and Prasant Mohapatra and Joseph Zambreno}
}
@article {PanZam12B,
	title = {Comments on {\textquoteright}Arithmetic Coding as a Non-Linear Dynamical System{\textquoteright}},
	journal = {Communications in Nonlinear Science and Numerical Simulation (CNSNS)},
	volume = {17},
	number = {12},
	year = {2012},
	pages = {4536-4543},
	abstract = {Nagaraj et al. [1, 2] present a skewed-non-linear Generalized Luroth Series (s-nGLS) framework. S-nGLS uses non-linear maps for GLS to introduce a security parameter a which is used to build a keyspace for image or data encryption. The map introduces non-linearity to the system to add an "encryption key parameter". The skew is added to achieve optimal compression efficiency. s-nGLS used as such for joint encryption and compression is a weak candidate, as explained in this communication. First, we show how the framework is vulnerable to known plaintext based attacks and that a key of size 256 bits can be broken within 1000 trials. Next, we demonstrate that the proposed non-linearity exponentially increases the hardware complexity of design. We also discover that s-nGlS can{\textquoteright}t be implemented as such for large bitstreams. Finally, we demonstrate how correlation of key  parameter with compression performance leads to further key vulnerabilities.},
	author = {Amit Pande and Joseph Zambreno and Prasant Mohapatra}
}
@article {PanZam12A,
	title = {Poly-DWT: Polymorphic Wavelet Hardware Support For Dynamic Image Compression},
	journal = {ACM Transactions on Embedded Computing Systems (TECS)},
	volume = {11},
	number = {1},
	year = {2012},
	abstract = {Many modern computing applications have been enabled through the use of real-time multimedia processing. While several hardware architectures have been proposed in the research literature to support such primitives, these fail to address applications whose performance and resource requirements have a dynamic aspect. Embedded multimedia systems typically need a power and computation efficient design in addition to good compression performance. In this paper, we introduce a Polymorphic Wavelet Architecture (Poly-DWT) as a crucial building block towards the development of embedded systems to address such challenges. We illustrate how our Poly-DWT architecture can potentially make dynamic resource allocation decisions, such as the internal bit representation and the processing kernel, according to the application requirements. We introduce a filter switching architecture that allows for dynamic switching between 5/3 and 9/7 wavelet filters and leads to a more power efficient design. Further, a multiplier-free design with a low adder requirement demonstrates the potential of Poly-DWT for embedded systems. Through an FPGA prototype, we perform a quantitative analysis of our Poly-DWT architecture, and compare our filter to existing approaches to illustrate the area and performance benefits inherent in our approach.
},
	author = {Amit Pande and Joseph Zambreno}
}
@conference {PanZam11B,
	title = {Architectures for Simultaneous Coding and Encryption using Chaotic Maps},
	booktitle = {Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
	year = {2011},
	month = {July},
	abstract = {In this work, we discuss an interpretation of arithmetic coding using chaotic maps. We present a hardware implementation using 64 bit fixed point arithmetic on Virtex-6 FPGA (with and without using DSP slices). The encoder resources are slightly higher than a traditional AC encoder, but there are savings in decoder performance. The architectures achieve clock frequency of 400-500 MHz on Virtex-6 xc6vlx75 device.},
	author = {Amit Pande and Joseph Zambreno and Prasant Mohapatra}
}
@article {PanZam11A,
	title = {Efficient Mapping and Acceleration of AES on Custom Multi-Core Architectures},
	journal = {Concurrency and Computation: Practice and Experience},
	volume = {23},
	number = {4},
	year = {2011},
	pages = {372-389},
	abstract = {Multi-core processors can deliver significant performance benefits for multi-threaded software by adding processing power with minimal latency, given the proximity of the processors. Cryptographic applications are inherently complex and involve large computations. Most cryptographic operations can be translated into logical operations, shift operations, and table look-ups. In this paper we design a novel processor (called -core) with a reconfigurable Arithmetic Logic Unit, and design custom two-dimensional multicore architectures on top of it to accelerate cryptographic kernels. We propose an efficient mapping of instructions from the multi-core grid to the individual processor cores and illustrate the performance of AES-128E algorithm over custom-sized grids. The model was developed using Simulink and the performance analysis suggests a positive trend towards development of large multi-core (or multi--core) architectures to achieve high throughputs in cryptographic operations.},
	author = {Amit Pande and Joseph Zambreno}
}
@conference {PanZam11C,
	title = {Hardware Architecture for Simultaneous Arithmetic Coding and Encryption},
	booktitle = {Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA)},
	year = {2011},
	month = {July},
	abstract = {Arithmetic coding is increasingly being used in upcoming image and video compression standards such as JPEG2000, and MPEG-4/H.264 AVC and SVC standards. It provides an efficient way of lossless compression and recently, it has been used for joint compression and encryption of video data. In this paper, we present an interpretation of arithmetic coding using chaotic maps. This interpretation greatly reduces the hardware complexity of decoder to use a single multiplier by using an alternative algorithm and enables encryption of video data at negligible computational cost. The encoding still requires two multiplications. Next, we present a hardware implementation using 64 bit fixed point arithmetic on Virtex-6 FPGA (with and without using DSP slices). The encoder resources are slightly higher than a traditional AC encoder, but there are savings in decoder performance. The architectures achieve clock frequency of 400-500 MHz on Virtex-6 xc6vlx75 device. We also advocate multiple symbol AC encoder design to increase throughput/slice of the device, obtaining a value of 4.},
	author = {Amit Pande and Joseph Zambreno and Prasant Mohapatra}
}
@conference {PanMoh11A,
	title = {Using Chaotic Maps for Encrypting Image and Video Content},
	booktitle = {Proceedings of the International Symposium on Multimedia (ISM)},
	year = {2011},
	month = {December},
	abstract = {Arithmetic Coding (AC) is widely used for the entropy coding of text and multimedia data. It involves recursive partitioning of the range [0,1) in accordance with the relative probabilities of occurrence of the input symbols. In this paper, we present a data (image or video) encryption scheme based on arithmetic coding, which we refer to as Chaotic Arithmetic Coding (CAC). In CAC, a large number of chaotic maps can be used to perform coding, each achieving Shannon optimal compression performance. The exact choice of map is governed by a key. CAC has the effect of scrambling the intervals without making any changes to the width of interval in which the codeword must lie, thereby allowing encryption without sacrificing any coding efficiency. We next describe Binary CAC (BCAC) with some simple Security Enhancement (SE) modes which can alleviate the security of scheme against known cryptanalysis against AC-based encryption techniques. These modes, namely Plaintext Modulation (PM), Pair-Wise Independent Keys (PWIK), and Key and ciphertext Mixing (MIX) modes have insignificant computational overhead, while BCAC decoder has lower hardware requirements than BAC coder itself, making BCAC with SE as excellent choice for deployment in secure embedded multimedia systems. A bit sensitivity analysis for key and plaintext is presented along with experimental tests for compression performance.},
	author = {Amit Pande and Prasant Mohapatra and Joseph Zambreno}
}
@conference {PanZam10B,
	title = {Design and Hardware Implementation of a Chaotic Encryption Scheme for Real-Time Embedded Systems},
	booktitle = {Proceedings of the IEEE Signal Processing and Communications Conference (SPCOM)},
	year = {2010},
	month = {July},
	abstract = {Chaotic encryption schemes are believed to provide a greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details using FPGA technology are provided. Logistic map is the simplest chaotic system and has a high potential to be used to design a stream cipher for real-time embedded systems. The cipher uses a pseudo-random sequence generator based on modified logistic map (MLM) and a random feedback scheme. MLM has better chaotic properties than the logistic map in terms of uniformity of bifurcation diagram and also avoids the stable orbits of logistic map, giving a more chaotic behavior to the system. The proposed cipher gives 16 bits of encrypted data per clock cycle. The hardware implementation results over Xilinx Virtex-6 FPGA give a synthesis clock frequency of 93 MHz and a throughput of 1.5 Gbps while using 16 hardware multipliers. This makes the cipher suitable for embedded devices which have tight constraints on power consumption, hardware resources and real-time parameters.},
	author = {Amit Pande and Joseph Zambreno}
}
@conference {PanZam10D,
	title = {Joint Video Compression and Encryption using Arithmetic Coding and Chaos},
	booktitle = {Proceedings of the IEEE International Conference on Internet Multimedia Systems Architecture and Applications (IMSAA)},
	year = {2010},
	month = {December},
	abstract = {Joint Video Compression and Encryption (JVCE) has gained increased attention in the past couple of years to reduce the computational complexity of video compression, as well as provide encryption of multimedia content for web services. In this paper, we present a JVCE framework based on Binary Arithmetic Coding (BAC). We first present an interpretation of BAC in terms of a skewed binary map and then describe 7 other possible chaotic maps which give similar Shannon optimal performance as BAC. We then propose a modification of BAC in which the overall length within the range [0,1) allocated to each symbol is preserved, but the choice of map used to encode each symbol is based on a key. The encoder, referred to as Chaotic Binary Arithmetic Coder (CBAC), has the effect of scrambling the intervals without making any changes to the width of interval in which the codeword must lie, thereby allowing encryption without sacrificing any coding efficiency. We also present some some security enhancement features to show how they can alleviate the limitations of our technique against known cryptanalysis on BAC-based encryption schemes.},
	author = {Amit Pande and Joseph Zambreno and Prasant Mohapatra}
}
@conference {PanZam10A,
	title = {A Reconfigurable Architecture for Secure Multimedia Delivery},
	booktitle = {Proceedings of the International Conference on VLSI Design (VLSID)},
	year = {2010},
	month = {January},
	abstract = {This paper introduces a reconfigurable architecture for ensuring secure and real-time video delivery through a novel parameterized construction of the Discrete Wavelet Transform (DWT). This parameterized construction promises multimedia encryption and is also well-suited to a hardware implementation due to our derivation of rational filter coefficients. We achieve an efficient and high-throughput reconfigurable hardware implementation through the use of LUT-based constant multipliers enabling run-time reconfiguration of encryption key. We also compare our prototype (using a Xilinx Virtex 4 FPGA) to several existing implementations in the research literature and show that we achieve superior performance as compared to both traditional CPU-based and custom VLSI approaches while adding features for secure multimedia delivery.},
	author = {Amit Pande and Joseph Zambreno}
}
@article {PanZam10E,
	title = {Reconfigurable Hardware Implementation of a Modified Chaotic Filter Bank Scheme},
	journal = {International Journal of Embedded Systems (IJES)},
	volume = {10},
	number = {3},
	year = {2010},
	pages = {248--258},
	abstract = {Chaotic filter bank schemes have been proposed in the research literature to allow for the efficient encryption of data for real-time embedded systems. Some security flaws have been  found in the underlying approaches which makes such a scheme unsafe for application in real life  scenarios. In this paper, we first present an improved scheme to alleviate the weaknesses of the  chaotic filter bank scheme, and add enhanced security features, to form a modified chaotic filter bank (MCFB) scheme. Next, we present a reconfigurable hardware implementation of the MCFB scheme. Implementation on reconfigurable hardware speeds up the performance of MCFB scheme by mapping some of the multipliers in design to reconfigurable look-up tables, while removing many unnecessary multipliers. An optimised implementation on Xilinx Virtex-5 XC5VLX330 FPGA gave a speedup of 30\% over non-optimised direct implementation. A clock frequency of 88 MHz was obtained. },
	author = {Amit Pande and Joseph Zambreno}
}
@article {PanZam10C,
	title = {The Secure Wavelet Transform},
	journal = {Springer Journal of Real-Time Image Processing (RTIP)},
	year = {2010},
	abstract = {There has been an increasing concern for the security of multimedia transactions over real-time embedded systems. Partial and selective encryption schemes have been proposed in the research literature, but these schemes significantly increase the computation cost leading to tradeoffs in system latency, throughput, hardware requirements and power usage. In this paper, we propose a lightweight multimedia encryption strategy based on a modified discrete wavelet transform (DWT) which we refer to as the secure wavelet transform (SWT). The SWT provides joint multimedia encryption and compression by two modifications over the traditional DWT implementations: (a) parameterized construction of the DWT and (b) subband re-orientation for the wavelet decomposition. The SWT has rational coefficients which allow us to build a high throughput hardware implementation on fixed point arithmetic. We obtain a zero-overhead implementation on custom hardware. Furthermore, a Look-up table based reconfigurable implementation allows us to allocate the encryption key to the hardware at run-time. Direct implementation on Xilinx Virtex FPGA gave a clock frequency of 60 MHz while a reconfigurable multiplier based design gave a improved clock frequency of 114 MHz. The pipelined implementation of the SWT achieved a clock frequency of 240 MHz on a Xilinx Virtex-4 FPGA and met the timing constraint of 500 MHz on a standard cell realization using 45 nm CMOS technology.},
	author = {Amit Pande and Joseph Zambreno}
}
@conference {PanZam09B,
	title = {An Efficient Hardware Architecture for Multimedia Encryption and Authentication using the Discrete Wavelet Transform},
	booktitle = {Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
	year = {2009},
	month = {May},
	pages = {85-90},
	abstract = {This paper introduces a zero-overhead encryption and authentication scheme for real-time embedded multimedia systems. The parameterized construction of the Discrete Wavelet Transform (DWT) compression block is used to introduce a free parameter in the design. It allows building a keyspace for lightweight multimedia encryption. The parameterization yields rational coefficients leading to an efficient fixed point hardware implementation. A clock speed of over 240 MHz was achieved on a Xilinx Virtex 5 FPGA. Comparison with existing approaches was performed to indicate the high throughput and low hardware overhead in adding the security feature to the DWT architecture.},
	author = {Amit Pande and Joseph Zambreno}
}
@conference {PanZam09C,
	title = {Efficient Translation of Algorithmic Kernels on Large-Scale Multi-Cores},
	booktitle = {Proceedings of the International Workshop on Reconfigurable and Multicore Embedded Systems (WoRMES)},
	year = {2009},
	month = {August},
	abstract = {In this paper we present the design of a novel embedded processor architecture (which we call a {\textmu}-core) that makes use of a reconfigurable ALU. This core serves as the basis of custom 2-dimensional array architectures that can be used to accelerate algorithms such as cryptography and image processing. An efficient translation and mapping of instructions from the multi-core grid to the individual processor cores is proposed and illustrated with an implementation of the AES encryption algorithm on custom-sized grids. A simulation model was developed using Simulink and the performance analysis suggests a positive trend towards the development and utilization of such hardware.},
	author = {Amit Pande and Joseph Zambreno}
}
@conference {PanZam08A,
	title = {Design and Analysis of Efficient Reconfigurable Wavelet Filters},
	booktitle = {Proceedings of the IEEE International Conference on Electro/Information Technology (EIT)},
	year = {2008},
	month = {May},
	abstract = {Real-time image and multimedia processing applications such as video surveillance and telemedicine can have dynamic requirements of system latency, throughput, and power consumption. In this paper we discuss the design of reconfigurable wavelet filters for image processing applications that can meet such dynamic requirements. We generate several efficient hardware designs based on a derived family of bi-orthogonal 9/7 filters. An efficient folded and multiplier-free implementation of a 9/7 filter is obtained with the help of nine adders, which is a significant improvement over other existing approaches. We also propose an architecture that allows for on-the-fly switching between 9/7 and 5/3 filter structures. A performance comparison of these filters and their hardware requirements with other existing approaches demonstrates the suitability of our choice.},
	author = {Amit Pande and Joseph Zambreno}
}
@conference {PanZam08B,
	title = {Polymorphic Wavelet Architectures using Reconfigurable Hardware},
	booktitle = {Proceedings of the International Conference on Field-Programmable Logic and its Applications (FPL)},
	year = {2008},
	month = {September},
	pages = {471-474},
	abstract = {Traditional microprocessor-based solutions are insufficient to serve the dynamic throughput demands of real-time scalable multimedia processing systems. This paper introduces a Polymorphic Architecture for the Discrete Wavelet Transform (Poly-DWT) as a building block of reconfigurable systems to address these needs. We illustrate how our PolyDWT architecture can dynamically make resource allocation decisions according to application requirements. We perform a quantitative analysis of our Poly-DWT architecture using an FPGA prototype, and compare our filters to existing approaches to illustrate the area and performance benefits inherent in our approach.},
	author = {Amit Pande and Joseph Zambreno}
}
