
@article {NelTow16A,
	title = {RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing},
	journal = {IEEE Transactions on Parallel and Distributed Systems (TPDS)},
	volume = {27},
	year = {2016},
	abstract = {The alignment of many short sequences of DNA, called reads, to a long reference genome is a common task in molecular biology. When the problem is expanded to handle typical workloads of billions of reads, execution time becomes critical. In this paper we present a novel reconfigurable architecture for minimal perfect sequencing (RAMPS). While existing solutions attempt to align a high percentage of the reads using a small memory footprint, RAMPS focuses on performing fast exact matching. Using the human genome as a reference, RAMPS aligns short reads hundreds of thousands of times faster than current software implementations such as SOAP2 or Bowtie, and about a thousand times faster than GPU implementations such as SOAP3.  Whereas other aligners require hours to preprocess reference genomes, RAMPS can preprocess the reference human genome in a few minutes, opening the possibility of using new reference sources that are more genetically similar to the newly sequenced data.},
	author = {Chad Nelson and Kevin Townsend and Osama Attia and Phillip Jones and Joseph Zambreno}
}
@conference {AttGri15A,
	title = {Accelerating All-Pairs Shortest Path Using A Message-Passing Reconfigurable Architecture},
	booktitle = {Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
	year = {2015},
	month = {December},
	abstract = {In this paper, we study the design and implementation of a reconfigurable architecture for graph processing algorithms. The architecture uses a message-passing model targeting shared-memory multi-FPGA platforms. We take advantage of our architecture to showcase a parallel implementation of the all-pairs shortest path algorithm (APSP) for unweighted directed graphs. Our APSP implementation adopts a fine-grain processing methodology while attempting to minimize  communication and synchronization overhead. Our design utilizes 64 parallel kernels for vertex-centric processing. We evaluate a prototype of our system on a Convey HC-2 high performance computing platform, in which our performance results demonstrates an average speedup of 7.9x over the sequential APSP algorithm and an average speedup of 2.38x over a multi-core implementation. 
},
	author = {Osama Attia and Alex Grieve and Kevin Townsend and Phillip Jones and Joseph Zambreno}
}
@conference {TowSun15A,
	title = {k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator},
	booktitle = {Proceedings of the IEEE International Conference on Electro/Information Technology (EIT)},
	year = {2015},
	month = {May},
	abstract = {Text classification is an important enabling technology for a wide range of applications such as Internet search, email filtering, network intrusion detection, and data mining electronic documents in general. The k Nearest Neighbors (k-NN) text classification algorithm is among the most accurate classification approaches, but is also among the most computationally expensive. In this paper, we propose accelerating k-NN using a novel reconfigurable hardware based architecture. More specifically, we accelerate a k-NN application{\textquoteright}s core with an FPGA-based sparse matrix vector multiplication coprocessor. On average our implementation shows a speed up factor of 15 over a naive single threaded CPU implementation of k-NN text classification for our datasets, and a speed up factor of 1.5 over a 32-threaded parallelized CPU implementation.},
	author = {Kevin Townsend and Song Sun and Tyler Johnson and Osama Attia and Phillip Jones and Joseph Zambreno}
}
@article {AttTow15A,
	title = {A Reconfigurable Architecture for the Detection of Strongly Connected Components},
	journal = {ACM Transactions on Reconfigurable Technology and Systems (TRETS)},
	volume = {9},
	year = {2015},
	month = {December},
	abstract = {The Strongly Connected Components (SCC) detection algorithm serves as a keystone for many graph analysis applications. The SCC execution time for large-scale graphs, as with many other graph algorithms, is dominated by memory latency. In this paper, we investigate the design of a parallel hardware architecture for the detection of SCCs in directed graphs. We propose a design methodology that alleviates memory latency and problems with irregular memory access. The design is composed of 16 processing elements dedicated to parallel Breadth-First Search (BFS) and 8 processing elements dedicated to finding intersection in parallel. Processing elements are organized to reuse resources and utilize memory bandwidth efficiently. We demonstrate a prototype of our design using the Convey HC-2 system, a commercial high-performance reconfigurable computing coprocessor. Our experimental results show a speedup of as much as 17x for detecting SCCs in large-scale graphs when compared to a conventional sequential software implementation.},
	author = {Osama Attia and Kevin Townsend and Phillip Jones and Joseph Zambreno}
}
@article {TowAtt16A,
	title = {A Scalable Unsegmented Multi-port Memory for FPGA-based Systems},
	journal = {International Journal of Reconfigurable Computing (IJRC)},
	volume = {2015},
	year = {2015},
	month = {December},
	abstract = {On-chip multi-port memory cores are crucial primitives for many modern high performance reconfigurable architectures and  multi-core systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage  capacity of the memory. In this paper, we present two approaches for designing multi-port memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multi-port memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.
},
	author = {Kevin Townsend and Osama Attia and Phillip Jones and Joseph Zambreno}
}
@conference {AttJoh14A,
	title = {CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search},
	booktitle = {Proceedings of the Reconfigurable Architectures Workshop (RAW)},
	year = {2014},
	month = {May},
	abstract = {Large-scale graph structures are considered a keystone for many emerging high-performance computing applications in which Breadth-First Search (BFS) is an important building block. For such graph structures, BFS operations tends to be memory-bound rather than compute-bound. In this paper, we present an efficient reconfigurable architecture for parallel BFS that adopts new optimizations for utilizing memory bandwidth. Our architecture utilizes a custom graph representation based on compressed-sparse raw format (CSR), as well as a restructuring of the conventional BFS algorithm. By taking maximum advantage of available memory bandwidth, our architecture continuously keeps our processing elements active. Using a commercial high-performance reconfigurable computing system (the Convey HC-2), our results demonstrate a 5x speedup over previously published FPGA-based implementations.
},
	author = {Osama Attia and Tyler Johnson and Kevin Townsend and Phillip Jones and Joseph Zambreno}
}
