
@conference {PanZam09C,
	title = {Efficient Translation of Algorithmic Kernels on Large-Scale Multi-Cores},
	booktitle = {Proceedings of the International Workshop on Reconfigurable and Multicore Embedded Systems (WoRMES)},
	year = {2009},
	month = {August},
	abstract = {In this paper we present the design of a novel embedded processor architecture (which we call a {\textmu}-core) that makes use of a reconfigurable ALU. This core serves as the basis of custom 2-dimensional array architectures that can be used to accelerate algorithms such as cryptography and image processing. An efficient translation and mapping of instructions from the multi-core grid to the individual processor cores is proposed and illustrated with an implementation of the AES encryption algorithm on custom-sized grids. A simulation model was developed using Simulink and the performance analysis suggests a positive trend towards the development and utilization of such hardware.},
	author = {Amit Pande and Joseph Zambreno}
}
