k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator

AuthorsKevin Townsend, Song Sun, Tyler Johnson, Osama Attia, Phillip Jones, and Joseph Zambreno
TypeConference Paper
Published inProceedings of the IEEE International Conference on Electro/Information Technology (EIT)
DateMay 2015

Abstract

Text classification is an important enabling technology for a wide range of applications such as Internet search, email filtering, network intrusion detection, and data mining electronic documents in general. The k Nearest Neighbors (k-NN) text classification algorithm is among the most accurate classification approaches, but is also among the most computationally expensive. In this paper, we propose accelerating k-NN using a novel reconfigurable hardware based architecture. More specifically, we accelerate a k-NN application’s core with an FPGA-based sparse matrix vector multiplication coprocessor. On average our implementation shows a speed up factor of 15 over a naive single threaded CPU implementation of k-NN text classification for our datasets, and a speed up factor of 1.5 over a 32-threaded parallelized CPU implementation.

BibTeX

@conference{TowSun15A,
  title = {k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator},
  booktitle = {Proceedings of the IEEE International Conference on Electro/Information Technology (EIT)},
  year = {2015},
  month = may,
  author = {Townsend, Kevin and Sun, Song and Johnson, Tyler and Attia, Osama and Jones, Phillip and Zambreno, Joseph}
}

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