A Reconfigurable Platform for Frequent Pattern Mining

AuthorsSong Sun, Michael Steffen, and Joseph Zambreno
TypeConference Paper
Published inProceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)
DateDecember 2008

Abstract

In this paper, a new hardware architecture for frequent pattern mining based on a systolic tree structure is proposed. The goal of this architecture is to mimic the internal memory layout of the original FP-growth algorithm while achieving a much higher throughput. We also describe an embedded platform implementation of this architecture along with detailed analysis of area requirements and performance results for different configurations. Our results show that with an appropriate selection of tree size, the reconfigurable platform can be several orders of magnitude faster than the FP-growth algorithm

BibTeX

@conference{SunSte08A,
  title = {A Reconfigurable Platform for Frequent Pattern Mining},
  booktitle = {Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
  year = {2008},
  month = dec,
  author = {Sun, Song and Steffen, Michael and Zambreno, Joseph}
}

← All publications