Efficient Mapping and Acceleration of AES on Custom Multi-Core Architectures
| Authors | Amit Pande and Joseph Zambreno |
|---|---|
| Type | Journal Article |
| Journal | Concurrency and Computation: Practice and Experience |
| Volume | 23 |
| Issue | 4 |
| Pages | 372-389 |
| Date | 2011 |
Abstract
Multi-core processors can deliver significant performance benefits for multi-threaded software by adding processing power with minimal latency, given the proximity of the processors. Cryptographic applications are inherently complex and involve large computations. Most cryptographic operations can be translated into logical operations, shift operations, and table look-ups. In this paper we design a novel processor (called -core) with a reconfigurable Arithmetic Logic Unit, and design custom two-dimensional multicore architectures on top of it to accelerate cryptographic kernels. We propose an efficient mapping of instructions from the multi-core grid to the individual processor cores and illustrate the performance of AES-128E algorithm over custom-sized grids. The model was developed using Simulink and the performance analysis suggests a positive trend towards development of large multi-core (or multi--core) architectures to achieve high throughputs in cryptographic operations.
BibTeX
@article{PanZam11A,
title = {Efficient Mapping and Acceleration of AES on Custom Multi-Core Architectures},
journal = {Concurrency and Computation: Practice and Experience},
volume = {23},
number = {4},
year = {2011},
pages = {372-389},
author = {Pande, Amit and Zambreno, Joseph}
}