Design and Hardware Implementation of a Chaotic Encryption Scheme for Real-Time Embedded Systems
| Authors | Amit Pande and Joseph Zambreno |
|---|---|
| Type | Conference Paper |
| Published in | Proceedings of the IEEE Signal Processing and Communications Conference (SPCOM) |
| Date | July 2010 |
Abstract
Chaotic encryption schemes are believed to provide a greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details using FPGA technology are provided. Logistic map is the simplest chaotic system and has a high potential to be used to design a stream cipher for real-time embedded systems. The cipher uses a pseudo-random sequence generator based on modified logistic map (MLM) and a random feedback scheme. MLM has better chaotic properties than the logistic map in terms of uniformity of bifurcation diagram and also avoids the stable orbits of logistic map, giving a more chaotic behavior to the system. The proposed cipher gives 16 bits of encrypted data per clock cycle. The hardware implementation results over Xilinx Virtex-6 FPGA give a synthesis clock frequency of 93 MHz and a throughput of 1.5 Gbps while using 16 hardware multipliers. This makes the cipher suitable for embedded devices which have tight constraints on power consumption, hardware resources and real-time parameters.
BibTeX
@conference{PanZam10B,
title = {Design and Hardware Implementation of a Chaotic Encryption Scheme for Real-Time Embedded Systems},
booktitle = {Proceedings of the IEEE Signal Processing and Communications Conference (SPCOM)},
year = {2010},
month = jul,
author = {Pande, Amit and Zambreno, Joseph}
}