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A
O. Attia, A. Grieve, K. Townsend, P. Jones and J. Zambreno, "Accelerating All-Pairs Shortest Path Using A Message-Passing Reconfigurable Architecture", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2015.  
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C. Kumar, S. Vyas, R. Cytron, C. Gill, J. Zambreno and P. Jones, "Cache Design for Mixed Critical Real-Time Systems", Proceedings of the International Conference on Computer Design (ICCD), October, 2014.  
M. Sayed and P. Jones, "Characterizing Non-Ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-based Thermometers", Proceedings of the International Conference on Reconfigurable Computing and FPGAs (Reconfig), November, 2011.  
J. Rilling, D. Graziano, J. Hitchcock, T. Meyer, X. Wang, P. Jones and J. Zambreno, "Circumventing a Ring Oscillator Approach to FPGA-Based Hardware Trojan Detection", Proceedings of the International Conference on Computer Design (ICCD), October, 2011.  
X. Wang, P. Jones and J. Zambreno, "A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns", ACM Computer Architecture News (CAN), vol. 43, issue 4, September, 2015.  
X. Wang, P. Jones and J. Zambreno, "A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns", Proceedings of the International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies (HEART), June, 2015.  
O. Attia, T. Johnson, K. Townsend, P. Jones and J. Zambreno, "CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2014.  
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A. Mills, S. Vyas, M. Patterson, C. Sabotta, P. Jones and J. Zambreno, "Design and Evaluation of a Delay-Based FPGA Physically Unclonable Function", Proceedings of the International Conference on Computer Design (ICCD), September, 2012.  
P. Zhang, A. Mills, J. Zambreno and P. Jones, "The Design and Integration of a Software Configurable and Parallelized Coprocessor Architecture for LQR Control", Journal of Parallel and Distributed Computing (JPDC), 2017.  
E
P. Zhang, J. Zambreno and P. Jones, "An Embedded Scalable Linear Model Predictive Hardware-based Controller using ADMM", Proceedings of the International Conference on Application-specific Systems, Architectures and Processors (ASAP), July, 2017.  
A. Gupte and P. Jones, "An Evaluation of a Slice Fault Aware Tool Chain", Proceedings of Design, Automation, and Test in Europe (DATE), March, 2010.  
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A. Gupte, S. Vyas and P. Jones, "A Fault-aware Toolchain Approach for FPGA Fault Tolerance", ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 20, no. 2, 2015.  
T. Johnson, D. Roggow, P. Jones and J. Zambreno, "An FPGA Architecture for the Recovery of WPA/WPA2 Keys", Journal of Circuits, Systems, and Computers (JCSC), vol. 24, issue 7, 2015.  
S. Vyas, C. Kumar, J. Zambreno, C. Gill, R. Cytron and P. Jones, "An FPGA-based Plant-on-Chip Platform for Cyber-Physical System Analysis", IEEE Embedded Systems Letters (ESL), vol. 6, no. 1, pp. 4-7, 2014.  
H
S. Vyas, A. Gupte, C. Gill, R. Cytron, J. Zambreno and P. Jones, "Hardware Architectural Support for Control Systems and Sensor Processing", ACM Transactions on Embedded Computing Systems (TECS), vol. 13, no. 2, 2013.  
C. Kumar, S. Vyas, R. Cytron, C. Gill, J. Zambreno and P. Jones, "Hardware-Software Architecture for Priority Queue Management in Real-time and Embedded Systems", International Journal of Embedded Systems (IJES), vol. 6, no. 4, pp. 319-334, 2014.  
K. Townsend, P. Jones and J. Zambreno, "A High Performance Systolic Architecture for k-NN Classification", Proceedings of the International Conference on Formal Methods and Models for Codesign (MEMOCODE), October, 2014.  
A. Gupte and P. Jones, "Hotspot Mitigation using Dynamic Partial Reconfiguration for Improved Performance", Proceedings of the International Conference on Reconfigurable Computing and FPGAs (Reconfig), December, 2009.  
I
C. Kumar, S. Vyas, J. Shidal, R. Cytron, C. Gill, J. Zambreno and P. Jones, "Improving System Predictability and Performance via Hardware Accelerated Data Structures", Proceedings of Dynamic Data Driven Application Systems (DDDAS), June, 2012.  
M. Steffen, P. Jones and J. Zambreno, "Introducing Graphics Processing from a Systems Perspective: A Hardware / Software Approach", Proceedings of the Annual Conference of the American Society for Engineering Education (ASEE), June, 2012.  
S. Sun, M. Monga, P. Jones and J. Zambreno, "An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs", IEEE Transactions on Circuits and Systems-I (TCAS-I), vol. 59, no. 1, pp. 113-123, 2012.  
K
K. Townsend, S. Sun, T. Johnson, O. Attia, P. Jones and J. Zambreno, "k-NN Text Classification using an FPGA-Based Sparse Matrix Vector Multiplication Accelerator", Proceedings of the IEEE International Conference on Electro/Information Technology (EIT), May, 2015.  
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M. Qasaimeh, P. Jones and J. Zambreno, "A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2017.  
P
A. Mills, P. Jones and J. Zambreno, "Parameterizable FPGA-based Kalman Filter Coprocessor Using Piecewise Affine Modeling", Proceedings of the Reconfigurable Architectures Workshop (RAW), May, 2016.  
D. Roggow, P. Uhing, P. Jones and J. Zambreno, "A Project-Based Embedded Systems Design Course Using a Reconfigurable SoC Platform", Proceedings of the International Conference on Microelectronic Systems Education (MSE), May, 2015.  
R
C. Nelson, K. Townsend, O. Attia, P. Jones and J. Zambreno, "RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing", IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 27, issue 10, 2016.  
O. Attia, K. Townsend, P. Jones and J. Zambreno, "A Reconfigurable Architecture for the Detection of Strongly Connected Components", ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol. 9, issue 2, December, 2015.  
X. Wang, P. Jones and J. Zambreno, "A Reconfigurable Architecture for QR Decomposition Using A Hybrid Approach", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2014.  
S
K. Townsend, O. Attia, P. Jones and J. Zambreno, "A Scalable Unsegmented Multi-port Memory for FPGA-based Systems", International Journal of Reconfigurable Computing (IJRC), vol. 2015, December, 2015.  
C. Kumar, S. Vyas, R. Cytron, C. Gill, J. Zambreno and P. Jones, "Scheduling Challenges in Mixed Critical Real-time Heterogeneous Computing Platforms", Proceedings of Dynamic Data Driven Application Systems (DDDAS), June, 2013.  
C. Nelson, K. Townsend, B S. Rao, P. Jones and J. Zambreno, "Shepard: A Fast Exact Match Short Read Aligner", Proceedings of the International Conference on Formal Methods and Models for Codesign (MEMOCODE), July, 2012.  
P. Zhang, A. Mills, J. Zambreno and P. Jones, "A Software Configurable and Parallelized Coprocessor Architecture for LQR Control", Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), December, 2015.  
A. Mills, P. Zhang, S. Vyas, J. Zambreno and P. Jones, "A Software Configurable Coprocessor-Based State-Space Controller", Proceedings of the International Symposium on Field-Programmable Logic and Applications (FPL), September, 2015.  
T
M. Steffen, P. Jones and J. Zambreno, "Teaching Graphics Processing and Architecture using a Hardware Prototyping Approach", Proceedings of the International Conference on Microelectronic Systems Education (MSE), June, 2011.  
A. Gupte and P. Jones, "Towards Hardware Support for Common Sensor Processing Tasks", Proceedings of the International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), August, 2009.