|Title||Design and Evaluation of a Hardware Accelerated Ray Tracing Data Structure|
|Publication Type||Conference Papers|
|Authors||M. Steffen and J. Zambreno|
|Conference Name||Proceedings of Theory and Practice of Computer Graphics (TPCG)|
The increase in graphics card performance and processor core count has allowed signiﬁcant performance acceleration for ray tracing applications. Future graphics architectures are expected to continue increasing the number of processor cores, further improving performance by exploiting data parallelism. However, current ray tracing implementations are based on recursive searches which involve multiple memory reads. Consequently, software implementations are used without any dedicated hardware acceleration. In this paper, we introduce a ray tracing method designed around hierarchical space subdivision schemes that reduces memory operations. In addition, parts of this traversal method can be performed in ﬁxed hardware running in parallel with programmable graphics processors.
We used a custom performance simulator that uses our traversal method, based on a kd-tree, to compare against a conventional kd-tree. The system memory requirements and system memory reads are analyzed in detail for both acceleration structures. We simulated six benchmark scenes and show a reduction in the number of memory reads of up to 70 percent compared to current recursive methods for scenes with over 100,000 polygons.