|Title||Architectures for Simultaneous Coding and Encryption using Chaotic Maps|
|Publication Type||Conference Papers|
|Authors||A. Pande, J. Zambreno and P. Mohapatra|
|Conference Name||Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI)|
In this work, we discuss an interpretation of arithmetic coding using chaotic maps. We present a hardware implementation using 64 bit ﬁxed point arithmetic on Virtex-6 FPGA (with and without using DSP slices). The encoder resources are slightly higher than a traditional AC encoder, but there are savings in decoder performance. The architectures achieve clock frequency of 400-500 MHz on Virtex-6 xc6vlx75 device.